Semiconductor Memory Device Pillar Vias for Stacked Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing manufacturing method for semiconductor memory devices with multiple stacked cell arrays faces challenges in cost increase and yield reduction due to increased etching on connecting portions of intermediate wiring layers, leading to unstable contacts and reduced processing margins.
Innovation Solution
The semiconductor memory device employs a method where pillar-shaped vias with stepwise cross-sections connect thicker, higher resistivity second wirings to first wirings, allowing for reduced lithography and etching processes while maintaining stable contacts through the use of thicker bit lines and word lines, which are formed with specific resistivity and grain size to ensure uniform sheet resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of cell arrays stacked is increased to improve integration degree, then productivity is improved, but device complexity increases leading to cost increase and yield reduction
Solution Approach 1:
Multiple vias are formed simultaneously through a single lithography and etching process. The via formation process merges the formation of vias for multiple wiring layers into one operation, reducing the total number of process steps while maintaining the ability to connect multiple stacked cell arrays
2Reliability
If via formation is performed for each wiring layer to ensure stable contact, then reliability is improved, but manufacturing precision deteriorates due to increased etching on connecting portions
Solution Approach 1:
A slit is formed in the connecting portion of the intermediate wiring layer before via formation. This preliminary action defines the via position and prevents excessive etching during the via formation process, thereby maintaining contact stability while improving manufacturing precision
Solution Approach 2:
The slit acts as an intermediary structure that guides the etching process. By providing a pre-formed opening, the slit mediates between the via formation process and the connecting portion, ensuring precise via placement without excessive material removal
3Ease of manufacture
If lithography and etching processes are reduced to lower cost and improve yield, then ease of manufacture is improved, but manufacturing precision deteriorates due to larger etching amounts
Solution Approach 1:
The slit is formed in advance in the connecting portion before via formation. This preliminary structuring allows the subsequent via etching to proceed with controlled depth and position, preventing gouging even though the via formation process is simplified and performed in a single step
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a cell array block having a plurality of cell arrays stacked therein, each of the cell arrays including a plurality of memory cells and a plurality of selective wirings selecting the plurality of memory cells are stacked, a pillar-shaped first via extending in a stack direction from a first height to a second height and having side surfaces connected to a first wiring, and a pillar-shaped second via extending in the stack direction from the first height to the second height and having side surfaces connected to a second wiring upper than the first wiring, the second wiring being thicker in the stack direction than the first wiring and having a higher resistivity than the first wiring.