Semiconductor Memory Planarization via Sacrificial Layer
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Solution Overview
Problem
The scaling down of DRAM cells with buried gates leads to defects due to limitations in fabrication technologies, necessitating an improved method for planarization that enhances performance and reliability without increasing complexity.
Innovation Solution
A method involving the formation of a sacrificial layer with a predetermined thickness to cover various regions of the semiconductor memory device, allowing for coplanar top surfaces and simplifying the planarization process by eliminating the need for initial mask layers, through a two-stepped removing process that ensures uniformity across regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional planarization process is used without a sacrificial layer, then the process flow is simpler, but the top surfaces of various regions are non-coplanar leading to defects
Solution Approach 1:
A sacrificial layer is formed in advance with a predetermined thickness to cover various regions of the semiconductor memory device. This preliminary action ensures that the top surfaces of the sacrificial layer are coplanar, which enables subsequent planarization processes to be performed directly without first forming mask layers, thus achieving both precision and simplicity
2Productivity
If mask layers are formed before planarization, then the planarization process is more controlled, but the overall process becomes more complex and time-consuming
Solution Approach 1:
The sacrificial layer is selectively removed through a removing process that removes the sacrificial layer, a portion of the second semiconductor layer and a portion of the insulating layer to expose the first semiconductor layer. This extraction eliminates the need for separate mask layers, simplifying the process flow while maintaining controlled planarization
Solution Approach 2:
The sacrificial layer serves as an intermediary structure that temporarily provides the necessary coplanarity during fabrication. After serving its purpose, it is removed through the removing process, leaving the desired coplanar top surfaces without requiring permanent mask layers
Data Source
AI summary
A method of forming semiconductor memory device including following steps. Firstly, a substrate having a memory cell region and a peripheral region is provided, and a first semiconductor layer is formed on the substrate within the periphery region. Next, an insulating layer and a second semiconductor layer are formed on the substrate, and the second semiconductor layer covers the substrate, the first semiconductor layer and the insulating layer. Then, a sacrificial layer is formed on the second semiconductor layer, wherein top surfaces of the sacrificial layer within the memory cell region and the periphery region are coplanar. Following these, a removing process is performed to remove the sacrificial layer, the second semiconductor layer and the insulating layer, to expose the first semiconductor layer. After that, a top surface of the first semiconductor layer is leveled with a top surface of the second semiconductor layer.