Semiconductor Memory Power Gating with Oxide Semiconductor Backup
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Solution Overview
Problem
The challenge is to reduce power consumption in semiconductor devices, particularly in integrated circuits (ICs), where increased operation frequency leads to higher dynamic power consumption and static power is dominated by leakage currents, hindering high performance and integration.
Innovation Solution
A memory device with a power management unit, cell array, and peripheral circuit is designed to implement multiple low power consumption modes, utilizing an oxide semiconductor transistor with a backup circuit for efficient power gating, allowing the device to selectively reduce power consumption by switching between modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating is implemented to reduce standby power, then power consumption is reduced, but data loss occurs in memory cells
Solution Approach 1:
The memory device is divided into multiple power domains (first power domain for peripheral circuits, second power domain for cell array). This segmentation allows independent power gating of different domains, enabling standby power reduction in the cell array while maintaining power supply to peripheral circuits for backup operations.
Solution Approach 2:
A backup circuit using oxide semiconductor transistors acts as an intermediary between the memory cell and the power gating mechanism. This backup circuit retains data even when the cell array is powered off, mediating between the need for power reduction and data retention requirements.
2Loss of energy
If multiple power domains are introduced to enable selective power gating, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple power domains (first power domain for peripheral circuits, second power domain for cell array). This segmentation allows independent power gating of different domains, enabling standby power reduction in the cell array while maintaining power supply to peripheral circuits for backup operations.
Solution Approach 2:
The power management unit serves multiple functions: it manages power supply to different domains, controls backup operations, and coordinates power gating sequences. This multi-functionality reduces the need for separate dedicated circuits for each function.
3Loss of energy
If backup circuit is added to each memory cell to enable power gating, then power consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The backup circuit utilizes oxide semiconductor transistors with specific material properties (extremely low off-state current) to achieve reliable data retention during power gating. By changing the transistor material parameter, the backup function is achieved with minimal additional circuit complexity.
Solution Approach 2:
The backup circuit is merged with the existing memory cell structure, sharing common elements such as word lines and bit lines. This integration reduces the overall manufacturing complexity compared to implementing separate backup systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces power consumption by enabling power gating and providing multiple low power modes, thereby minimizing leakage currents and optimizing performance and integration in semiconductor devices.
Implementation Method 1
A backup circuit capable of retaining data even when powered off, by taking advantage of a feature of extremely low off-state current of the OS transistor
Data Source
AI summary
Power consumption of a semiconductor device is reduced efficiently. The semiconductor device includes a power management unit, a cell array, and a peripheral circuit for driving the cell array. The cell array includes a word line, a bit line pair, a memory cell, and a backup circuit for backing up data in the memory cell. A row circuit and a column circuit are provided in a first power domain capable of power gating, and the cell array is provided in a second power domain capable of power gating. In the operation mode of a memory device, a plurality of low power consumption modes, which have lower power consumption than the standby mode, are set. The power management unit selects one from the plurality of low power consumption modes and performs control for bringing the memory device into the selected low power consumption mode.