Semiconductor Memory Device Separate Power Supply Terminals

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Solution Overview

Problem

The challenge in semiconductor memory devices is to maintain high productivity and speed while reducing memory cell size, as separate core and interface chips require different operation voltages during stress tests, posing a risk of damaging the interface chip due to mismatched voltage amplitudes and potential latch-up issues.

Innovation Solution

A semiconductor memory device design featuring separate core and interface chips with distinct power supply terminals, allowing for independent voltage application to each chip, and through-holes for voltage supply via through-electrodes, ensuring optimal voltages and matched signal amplitudes to prevent chip damage during stress tests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If separate chips are used for core section and interface section, then chip size is reduced and productivity is improved, but different voltage requirements cause damage risk during stress testing

Engineering Contradiction:

Improvechip manufacturing productivityVSAvoidinterface chip reliability during stress test

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The power supply system is segmented into separate power supply terminals for the core chip and interface chip, allowing independent voltage control. This segmentation enables the core chip to receive higher voltage during stress testing while the interface chip receives appropriate lower voltage, preventing damage while maintaining manufacturing productivity benefits.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different voltage levels are applied to different parts of the system (core chip vs. interface chip) based on their specific requirements. The core chip receives high voltage for stress testing while the interface chip receives optimized lower voltage, ensuring each component operates under appropriate electrical conditions during manufacturing processes.

Inventive Principle:

Principle #3Local quality

2Measurement precision

If high voltage is applied to core chip during stress test, then memory cell testing is improved, but interface chip transistors may be broken due to low withstand voltage

Engineering Contradiction:

Improvememory cell stress test accuracyVSAvoidtransistor damage to interface chip

Core Design Contradiction:

Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The power supply system is divided into separate terminals that can independently control voltage levels to the core chip and interface chip. This allows precise application of high voltage stress to memory cells while simultaneously protecting interface chip transistors by maintaining them at safe voltage levels during the same stress testing operation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Separate power supply terminals act as intermediaries between the external stress testing equipment and the chips. These intermediaries enable selective voltage application, allowing the stress test signal to reach the core chip at high voltage while the interface chip receives a mediated, reduced voltage level that prevents transistor breakdown.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Device complexity

If common power supply terminal is used for both chips, then device complexity is reduced, but optimal voltage cannot be given to each chip

Engineering Contradiction:

Improvepower supply terminal configurationVSAvoidvoltage optimization for each chip

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The power supply configuration is segmented into multiple independent terminals rather than using a single common terminal. This segmentation increases the adaptability of the system by allowing each chip to receive optimally tailored voltage levels, compensating for the increased complexity through improved functional versatility and chip-specific voltage optimization.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS7760573B2Semiconductor memory device and stress testing method thereof

Publication Date: 2010.07.20 LONGITUDE LICENSING LTD

AI summary

A semiconductor memory device includes a core chip having at least memory cells formed in the core chip, an interface chip having at least peripheral circuits of the memory cells formed in the interface chip, and an external terminal group. The external terminal group includes at least a core power supply terminal that is connected to an internal circuit of the core chip without being connected to an internal circuit of the interface chip, and an interface power supply terminal that is connected to an internal circuit of the interface chip without being connected to the internal circuit of the core chip. With this arrangement, mutually different operation voltages that are optimum for both chips can be given to these chips.