Semiconductor Memory Device Manufacturing Process Simplification
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Solution Overview
Problem
The complexity of manufacturing steps in resistance varying type memory devices leads to unclear cost benefits compared to three-dimensionally structured flash memory, and existing technologies face challenges in simplifying the manufacturing process while maintaining device performance.
Innovation Solution
The semiconductor memory device incorporates a memory cell array with standardized structures for both memory cells and select transistors, using integrated materials for the switching layer, tunnel barrier layer, channel layer, and gate insulating layer, which simplifies the manufacturing process by reducing the number of lithography steps and film depositions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If resistance varying type memory is used to achieve miniaturization and three-dimensional structure, then memory capacity and integration are improved, but manufacturing complexity increases making cost benefit unclear
Solution Approach 1:
The patent merges the manufacturing processes for memory cells and select transistors into a unified process. The same film deposition and lithography steps are used to form both the switching layer of memory cells and the channel layer of select transistors, eliminating the need for separate processing sequences and reducing overall manufacturing complexity
Solution Approach 2:
The patent creates multi-functional layers that serve dual purposes. The switching layer material and channel layer material are formed using identical materials and processes, allowing a single processing step to accomplish what previously required separate specialized steps for different device components
2Reliability
If separate manufacturing steps are used for memory cells and select transistors, then device performance is maintained, but manufacturing cost increases
Solution Approach 1:
The patent combines previously separate manufacturing steps into unified processes. The same film deposition, etching, and lithography steps that form memory cell structures also form select transistor structures, reducing the total number of manufacturing steps and associated costs while preserving device performance
Solution Approach 2:
The patent uses homogeneous materials and uniform processing conditions for both memory cells and select transistors. The switching layer and channel layer are formed using the same material system and deposition parameters, ensuring consistent device performance while simplifying manufacturing
Data Source
AI summary
A semiconductor memory device according to an embodiment includes: a substrate having a surface extending in a first direction and a second direction intersecting the first direction; and a memory cell array disposed above the substrate, the memory cell array having: a first wiring line extending in the first direction; a second wiring line extending in a third direction intersecting the first and second directions; a third wiring line extending in the second direction; a memory cell including a first layer provided in an intersection region of the first wiring line and the second wiring line; and a select transistor including a channel layer provided between the second wiring line and the third wiring line, the first layer of the memory cell including a first material which is an oxide, and the channel layer of the select transistor including the first material.