Local Re-crystallization Control for Semiconductor Memory Stability
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Solution Overview
Problem
In the fabrication of complex integrated circuits using CMOS technology, reducing transistor channel length to enhance performance leads to short channel effects and challenges in charge carrier mobility, particularly in memory areas where increased strain and crystalline defects can cause instability and yield loss.
Innovation Solution
The technique involves selectively applying strain-inducing mechanisms and amorphization processes in speed-critical logic blocks while modifying re-crystallization conditions in memory areas to maintain high strain levels without introducing dislocation defects, using stress memorization techniques and tilted amorphization to position defects away from critical areas, and optimizing crystallographic configurations for reduced lattice defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strain-inducing mechanisms and amorphization processes are applied to increase charge carrier mobility in the channel region, then transistor performance is improved, but dislocation defects and memory instability occur
Solution Approach 1:
The patent applies different re-crystallization conditions to different regions of the semiconductor device. Speed-critical logic blocks receive standard re-crystallization treatment to maximize transistor performance, while memory areas receive modified re-crystallization conditions (lower temperature, different duration) to prevent dislocation defects and maintain stability. This spatial differentiation of processing parameters resolves the contradiction between performance enhancement and defect prevention.
Solution Approach 2:
The patent modifies re-crystallization parameters (temperature, duration, atmospheric conditions) specifically for memory areas to prevent dislocation defect formation. By adjusting these physical parameters, the process maintains the beneficial strain effects while avoiding the harmful crystalline defects that would otherwise compromise memory stability.
2Speed
If channel length is reduced to enhance operating speed, then performance is improved, but short channel effects and controllability issues arise
Solution Approach 1:
The patent modifies the re-crystallization process parameters to control the crystalline structure and dopant distribution in the channel region. By optimizing temperature, duration, and atmospheric conditions, the process maintains sharp doping profiles and proper crystalline orientation even in scaled devices, thereby preserving channel controllability despite reduced channel length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance in speed-critical regions while maintaining stability in memory areas, allowing for increased strain without yield loss or operational instability, thus improving overall device performance.
Implementation Method 1
performing a first amorphization process for first N-channel transistors of a first device region of a semiconductor device
Implementation Method 2
annealing the first and second P-channel transistors and N-channel transistors in the presence of a material layer formed above the first device region so as to re-crystallize the first N-channel transistors in a strained state
Implementation Method 3
using stress memorization techniques and tilted amorphization to position defects away from critical areas
Implementation Method 4
performing a second amorphization process for second N-channel transistors of a memory device region, while masking the first device region, wherein the second amorphization process comprises an implantation step using a tilt angle for introducing an implantation species
Implementation Method 5
optimizing crystallographic configurations for reduced lattice defects
Data Source
AI summary
By appropriately locally controlling the conditions during a re-growth process in a memory region and a speed-critical device region, the creation of dislocation defects may be reduced in the memory region, thereby enhancing overall stability of respective memory cells. On the other hand, enhanced strain levels may be obtained in the speed-critical device region by performing an efficient amorphization process and re-crystallizing amorphized portions, for instance, in the presence of a rigid material to provide a desired high strain level.