3D Semiconductor Memory Read Control via Dual Carrier Injection
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Solution Overview
Problem
In three-dimensional semiconductor memory devices, defects near the interface between semiconductor pillars and gate insulating films lead to attenuated cell currents, making it difficult to properly read information due to electron traps and noise interference.
Innovation Solution
Applying voltage for both holes and electrons during the read process to increase cell current by causing hole and electron currents to flow near respective interfaces, thereby enhancing the distinguishability of ON/OFF states in memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional read methods are used in three-dimensional semiconductor memory devices, then the device structure can be maintained, but cell current is attenuated due to defects near the interface between semiconductor pillars and gate insulating films, making it difficult to properly read information
Solution Approach 1:
The patent applies voltage for both holes and electrons during the read process, changing the electrical parameters applied to the memory cell. By applying appropriate voltages to the control gate and bit line, the patent enhances cell current and improves the distinguishability of ON/OFF states, thereby resolving the contradiction between read accuracy and cell current stability
Solution Approach 2:
The patent employs a structured read process with periodic voltage application sequences. By systematically applying voltages to different terminals in specific sequences (applying voltage to control gate, then to bit line, and measuring current), the patent ensures reliable information reading despite interface defects
2Measurement precision
If voltage is applied to increase cell current, then the distinguishability of ON/OFF states improves, but the complexity of the control process increases
Solution Approach 1:
The patent segments the read process into distinct stages: first applying voltage to the control gate, then applying voltage to the bit line, and finally measuring the current. This segmentation of the control process makes the complex voltage application sequence more manageable and systematic, while still achieving improved state distinguishability
Solution Approach 2:
The patent applies voltage to the control gate before applying voltage to the bit line during the read process. This preliminary action prepares the memory cell by establishing the appropriate electrical conditions in advance, which simplifies the overall control process by creating a predictable sequence of operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases cell current, improving the ability to accurately read information from memory cells by reducing the influence of noise and fixed charge variations.
Implementation Method 1
Applying voltage for both holes and electrons during the read process to increase cell current by causing hole and electron currents to flow near respective interfaces
Data Source
AI summary
According to one embodiment, there is provided a semiconductor device including a first semiconductor region, a stacked body, a semiconductor channel, a gate insulating film, and a control circuit. The stacked body is of conductive films arranged in a stacking direction with an insulator interposed. The semiconductor channel penetrates the stacked body in the stacking direction, and is electrically connected at one end to the first semiconductor region. The gate insulating film is arranged between the stacked body and the semiconductor channel. The control circuit supplies a first voltage to a closest conductive film of the stacked body to the first semiconductor region, and supplies a second voltage higher than the first voltage to the first semiconductor region, at a time of reading information from one of memory cells formed at positions where the conductive films intersect with the semiconductor channel.