Semiconductor Memory Device Address Decoding and Redundancy
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Solution Overview
Problem
Semiconductor memory devices experience significant time loss due to the delay in decoding addresses and determining redundancy usage, which obstructs high-speed operation and reduces efficiency, especially with additive latency causing unnecessary delays in address processing.
Innovation Solution
Implementing a semiconductor memory device with a delay time selecting portion that synchronizes the internal read/write command with an external clock rising edge before address setup, allowing for immediate output of the final read/write command without delay when additive latency is not present, and using a decoder to determine redundancy usage before generating the internal read/write command.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the address decoding and redundancy determination are performed after generating the internal read/write command, then the command generation process is simplified, but the asynchronous access time increases due to unnecessary delays
Solution Approach 1:
The patent applies preliminary action by performing address decoding and redundancy determination before the internal read/write command is generated. The column address is decoded and redundancy is determined in advance during the additive latency period, so that when the command is generated, the final column address is already ready, eliminating unnecessary delays and reducing asynchronous access time.
2Reliability
If the internal read/write command is delayed to allow address decoding and redundancy determination, then the correctness of memory cell selection is ensured, but the operational speed decreases
Solution Approach 1:
The patent resolves this contradiction by performing the address decoding and redundancy determination as preliminary actions during the additive latency period. This ensures that the column address is fully processed and the correct memory cell selection is determined before the internal read/write command is generated, while simultaneously maintaining high operational speed by eliminating the need for additional delay.
Solution Approach 2:
The patent applies dynamics by making the command generation process adaptive based on when the address is applied. When the address is applied before the internal read/write command is generated, the system dynamically adjusts by performing decoding and redundancy determination in advance, optimizing both reliability and speed based on the timing conditions.
3Stability of the object's composition
If additive latency is used to synchronize commands with clock edges, then synchronous operation is achieved, but unnecessary delays are introduced when addresses are applied early
Solution Approach 1:
The patent applies preliminary action by utilizing the additive latency period productively to perform address decoding and redundancy determination before the internal read/write command is generated. This transforms the previously wasted delay time into useful processing time, maintaining synchronous operation while eliminating unnecessary delays in asynchronous access.
Solution Approach 2:
The patent applies parameter changes by modifying the timing relationship between address application and command generation. By changing when the address decoding and redundancy determination are performed (before command generation rather than after), the system optimizes the additive latency parameter to reduce unnecessary delays while maintaining synchronous operation stability.
Data Source
AI summary
A semiconductor memory device includes a delay time selecting portion for outputting, as a final read/write command, an internal read/write command that corresponds to an external read/write command and is synchronized with an external clock rising edge at a tRCD time without any delay when an address is applied before an address setup time based on the external clock rising edge of a previously set tRCD time, a decoder for decoding an address applied from an external portion with the read/write command to output a decoded address, and a selecting portion for receiving the decoded address to select a memory cell of a memory cell array in response to the final read/write command.