Semiconductor Memory Redundant Wiring Layer IR Drop
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Solution Overview
Problem
In semiconductor memory devices with multi-layer structures, the increased length of wiring at contact portions leads to higher resistance values, resulting in IR drop issues due to finer microfabrication of wiring pitches.
Innovation Solution
The implementation of a redundant wiring layer between the first and second wiring layers, with redundant wiring extending in the same direction as the third and fourth wirings, and connected by contacts along these directions, reduces connection resistance by allowing for finer line and space formations without increasing IR drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the wiring pitch is reduced for finer microfabrication, then the integration density is improved, but the connection resistance at contact portions increases due to longer wiring length in the stacking direction
Solution Approach 1:
The patent introduces a redundant wiring layer positioned between the first and second wiring layers, adding a dimensional element to the wiring structure. This intermediate layer provides alternative current paths that bypass the high-resistance contact portions, effectively reducing the overall connection resistance while maintaining the fine wiring pitch for high integration density
2Productivity
If the contact portion wiring length increases in the stacking direction, then the wiring pitch can be reduced, but the IR drop increases due to higher connection resistance
Solution Approach 1:
The patent segments the current path by introducing the redundant wiring layer as an intermediate conductive path. This segmentation divides the long high-resistance current path into shorter segments, with the redundant layer providing low-resistance shunt paths that reduce the overall IR drop while enabling finer wiring pitch for higher productivity
Data Source
AI summary
A semiconductor memory device includes a cell array layer including a first and a second wiring, which cross each other; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third and the fourth wiring, wherein the device further comprises a redundant wiring layer being formed between the first and the second wiring layer, the redundant wiring layer being formed with a redundant wiring having a portion extending in the same direction as at least one of the third and the fourth wiring, and the third and the redundant wiring, and the fourth and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third or the fourth wiring.