Semiconductor Memory Reference Voltage Control Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory holding characteristics deteriorate with fluctuations in power supply voltage, leading to reduced operating margins and inconsistent sensing, especially when the reference voltage is set lower than ½ VDD.
Innovation Solution
A semiconductor memory with a reference voltage control circuit that generates a reference voltage and includes a dummy-bit-line voltage generating circuit to control bit line voltages, allowing for stable reference voltage settings across varying power supply voltages, preventing unnecessary increases or decreases in reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference voltage Vref is set lower than ½ VDD to improve cell holding characteristics, then the cell holding characteristics are improved, but the reading margin decreases and sensing consistency deteriorates
Solution Approach 1:
The patent implements dynamic control of the reference voltage Vref based on the actual power supply voltage VDD. The reference voltage control circuit adjusts Vref in real-time according to VDD fluctuations, rather than using a fixed low reference voltage. This dynamic adjustment maintains optimal cell holding characteristics while ensuring sufficient reading margin and sensing consistency across varying operating conditions.
Solution Approach 2:
The patent changes the reference voltage parameter Vref dynamically based on the power supply voltage VDD. By establishing a proportional relationship between Vref and VDD (Vref = k × VDD where k is a control coefficient), the system adapts the reference voltage level to match actual operating conditions, resolving the contradiction between improved holding characteristics and maintained sensing precision.
2Measurement precision
If the reference voltage Vref fluctuates with power supply voltage VDD, then the reading margin improves, but the cell holding characteristics deteriorate
Solution Approach 1:
The patent implements a feedback control mechanism where the reference voltage control circuit continuously monitors the power supply voltage VDD and adjusts the reference voltage Vref accordingly. This feedback loop ensures that Vref changes in a controlled manner proportional to VDD fluctuations, maintaining both adequate reading margin and stable cell holding characteristics by preventing excessive reference voltage changes.
3Speed
If high-speed circuit operation is implemented, then the operating speed increases, but the digit disturb hold (DDH) characteristics deteriorate
Solution Approach 1:
The patent applies preliminary action by precharging the bit lines to a reference voltage Vref that is dynamically optimized based on the power supply voltage VDD before read operations. This precharging ensures that the bit lines start from an optimal voltage level, enabling high-speed operation while maintaining sufficient voltage margins to prevent digit disturb and preserve DDH characteristics.
Data Source
AI summary
Deterioration of holding characteristics due to fluctuations in power supply voltage VDD is prevented. During writing or reading in one of memory circuits, a pair of bit lines in the other memory circuit is controlled to a dummy-bit-line voltage ranging from a ground voltage to ½×VDD. In a subsequent precharge period, a pair of bit lines in one of the memory circuits and the pair of bit lines in the other memory circuit are coupled to a reference voltage generating circuit.