Semiconductor Memory Refresh Control Circuit
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Solution Overview
Problem
In portable devices, semiconductor memories with dynamic memory cells face inefficiencies in power consumption due to frequent changes in memory areas during self-refresh modes, leading to reduced system performance and ineffective power reduction.
Innovation Solution
A semiconductor memory system with a refresh register storing disable block information, a refresh control circuit executing periodic refresh operations for specific memory blocks, and a register control circuit writing this information during access cycles, optimally setting which memory blocks require refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory area is changed frequently by mode register set command to adapt to different operation states, then the adaptability to system operation states is improved, but the access efficiency deteriorates due to frequent changes during memory access cycles
Solution Approach 1:
The patent implements dynamic adaptation by allowing the memory area configuration to change during operation. The register control circuit enables flexible modification of the memory area specified in the refresh register without requiring mode register set commands, allowing the system to adapt to changing operation states while maintaining access efficiency through in-place updates during access cycles.
Solution Approach 2:
The memory device performs self-configuration by enabling the register control circuit to update the memory area setting internally during access cycles. This self-service mechanism eliminates the need for external mode register set commands to change memory areas, allowing the system to reconfigure itself without sacrificing access efficiency.
2Reliability
If the refresh operation is executed to all memory areas to ensure data integrity, then the reliability is improved, but the power consumption increases due to unnecessary refresh operations in unused memory areas
Solution Approach 1:
The patent applies local quality by enabling selective refresh operations on specific memory areas rather than uniformly refreshing the entire memory space. The refresh register stores disable block information that identifies which memory blocks should be excluded from refresh operations, allowing the system to maintain data integrity in active areas while saving power by skipping refresh operations in unused areas.
Solution Approach 2:
The system dynamically changes the refresh parameter by modifying which memory blocks are included in refresh operations based on current operation states. The register control circuit updates the memory area configuration to reflect current usage patterns, enabling the system to adjust refresh behavior from comprehensive to selective based on real-time conditions.
3Use of energy by stationary object
If the memory area is changed between access cycles to reduce power consumption, then the power consumption is reduced, but the system performance deteriorates due to the time required for area changes
Solution Approach 1:
The patent implements preliminary action by pre-configuring the memory area setting in the refresh register before power consumption reduction becomes necessary. The register control circuit is ready to update the memory area configuration at any time during access cycles, allowing the system to transition to low-power mode with the correct memory area already identified, eliminating delays associated with real-time area changes.
Data Source
AI summary
A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory blocks, the register control circuit writes the disable block information to the refresh register according to an external input. Consequently, in order to rewrite the refresh register, it is not necessary to use an additional operation cycle to the access cycle. Since there is no need to insert an extra operation cycle, it is possible to change a memory area to be refreshed without lowering effective efficiency of access cycles. As a result, power consumption can be reduced.