Semiconductor Memory Repair Using ECC Logic and Redundancy
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Solution Overview
Problem
Conventional redundancy repair techniques for semiconductor memory devices consume excessive resources and are inefficient due to the increasing number of defective memory cells, especially in volatile memory devices like DRAM, where a large amount of redundancy is required to replace single bit failures.
Innovation Solution
Implementing an error correction code (ECC) logic in semiconductor memory devices to detect and correct fail bits, allowing for efficient repair operations by determining whether to replace main repair units with redundant units based on correctable status and cumulative fail bit counts, thereby minimizing resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional redundancy repair technique is used to replace defective cells, then defective cells can be repaired, but a large amount of resources are unnecessarily consumed
Solution Approach 1:
The patent segments the repair process into two distinct approaches: ECC-based correction for correctable errors and redundancy replacement for uncorrectable errors. This segmentation allows the system to apply the appropriate repair method based on the error type, avoiding unnecessary resource consumption from replacing cells that could be corrected through ECC logic.
Solution Approach 2:
The patent changes the parameter of error handling by introducing correctable status determination. Instead of uniformly replacing all defective cells with redundancy, the system evaluates the correctable status of each fail bit and applies different repair strategies accordingly, optimizing resource utilization while maintaining repair effectiveness.
2Reliability
If redundancy is increased to replace single bit failures, then repair capability is improved, but the size of memory device increases
Solution Approach 1:
The patent applies partial action by using redundancy only when necessary - specifically for uncorrectable errors that ECC logic cannot handle. For correctable errors, the system uses ECC-based correction without invoking redundancy mechanisms, thereby reducing the overall redundancy requirements and minimizing memory device size while maintaining adequate repair capability.
3Reliability
If row or column redundancy circuit is configured to replace rows for each row group or columns for each column group, then defective cells can be repaired, but a large amount of resources are unnecessarily consumed
Solution Approach 1:
The patent performs preliminary action by determining the correctable status of fail bits through ECC logic before initiating redundancy replacement. This preliminary evaluation prevents unnecessary redundancy allocation for correctable errors, optimizing the usage of redundancy resources while ensuring that only truly necessary replacements are performed.
Data Source
AI summary
A repair method of a semiconductor memory device which includes a memory cell array including a main and a redundant cell array and error correction code (ECC) logic includes detecting a fail bit of each of a main repair unit of the main cell array and a redundant repair unit of the redundant cell array, determining whether the fail bit detected from each of the main and redundant repair units is correctable, by using the ECC logic and determining a first or a second correctable status, calculating a first cumulative correctable fail bit count of each of the main repair unit and the redundant repair unit, and determining whether to replace the main repair unit with the redundant repair unit depending on the first correctable status, the second correctable status, and the first and second cumulative correctable fail bit counts and performing a repair operation depending on the determination result.