Semiconductor Memory Resistance Estimation via Dummy Blocks
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in easily estimating the resistance value of wiring connected to a NAND string, which hinders efficient design and development, and increases chip area and development costs.
Innovation Solution
The semiconductor memory design includes a structure with alternating stacks of insulators and conductors, where the resistance value of select gate lines and word lines can be estimated by measuring the resistance between contacts separated by slits, allowing for reduced chip area and development costs without significant design changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional semiconductor memory structures are used, then manufacturing processes are well-established, but resistance value estimation of wiring becomes difficult and chip area increases
Solution Approach 1:
The memory cell array is divided into multiple blocks, with specific blocks designated as dummy blocks that contain wiring structures identical to active blocks. This segmentation allows resistance measurement to be performed on isolated wiring portions without interfering with active memory operations, enabling accurate resistance estimation while maintaining compact chip area.
Solution Approach 2:
Dummy blocks serve as intermediary structures that replicate the wiring configuration of active blocks. By measuring resistance in these dummy blocks, the resistance characteristics of the actual memory wiring can be estimated without directly accessing or disrupting the active memory cells, thus preventing chip area expansion while achieving measurement precision.
2Measurement precision
If resistance measurement structures are added to estimate wiring resistance, then measurement capability improves, but device complexity and development costs increase
Solution Approach 1:
The dummy blocks perform multiple functions: they replicate the wiring structure for resistance measurement purposes, maintain the alternating stack configuration consistent with active blocks, and provide test structures without requiring additional measurement equipment or complex external fixtures. This multi-functionality improves measurement precision while avoiding increased device complexity.
Solution Approach 2:
The memory device contains built-in dummy blocks that automatically provide the measurement function. The alternating stack structure and wiring configuration within dummy blocks are self-contained, allowing resistance measurement to be performed using standard equipment without requiring complex external measurement systems, thus improving measurement capability without increasing overall device complexity.
Data Source
AI summary
A semiconductor memory includes a substrate and an alternating stack of first insulators and first conductors above the substrate. First to third regions are provided in this order along a direction parallel to a surface of the substrate. The alternating stack is in a dummy region at part of each of the first to third regions. Second and third conductors extend in parallel to each other in the direction above a top one of the first conductors. A plurality of first pillars extend through the second conductor. A plurality of second pillars extend through the third conductor. A columnar first contact is provided on the second conductor in the first region, and a columnar second contact is provided on the third conductor in the first region. The second and third conductors are separated from each other in the first and second regions, and connected to each other in the third region.