Semiconductor Memory Sensing With Size-Based Resistance Adjustment
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Solution Overview
Problem
The integration and operational reliability of semiconductor devices are limited by the area occupied by unit memory cells, especially in three-dimensional structures, where variations in memory string sizes affect current flow and read operations.
Innovation Solution
A semiconductor device with memory strings of different sizes, connected to bit lines, and a page buffer that adjusts resistance and evaluation periods based on memory string size to improve operational reliability and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are stacked in a three-dimensional structure to improve integration, then the degree of integration is improved, but variations in memory string sizes cause inconsistencies in current flow and read operations
Solution Approach 1:
The patent applies dynamics by making the evaluation period adjustable rather than fixed. The page buffer dynamically extends or shortens the evaluation period based on the detected memory string size, allowing the system to adapt to variations in memory string characteristics while maintaining consistent read operation performance across different string sizes in the three-dimensional structure
Solution Approach 2:
The patent changes the parameter of evaluation period duration based on memory string size. By detecting the actual size of the memory string and adjusting the evaluation period accordingly, the system compensates for variations in current flow characteristics caused by different string sizes, thereby maintaining operational reliability while preserving high integration
2Device complexity
If a fixed evaluation period is used in the page buffer, then the device complexity is reduced, but read operation consistency deteriorates across memory strings of different sizes
Solution Approach 1:
The patent applies preliminary action by detecting the memory string size before the read operation and using this information to determine the appropriate evaluation period. This preliminary detection and adjustment ensures that the evaluation period is optimized for each specific memory string, guaranteeing consistent read operation results across all string sizes without requiring complex real-time adjustments during the read process
Solution Approach 2:
The patent implements feedback by detecting the actual size of the memory string and using this feedback information to adjust the evaluation period. The page buffer monitors the memory string characteristics and modifies the evaluation period accordingly, creating a closed-loop system that maintains read operation consistency while managing complexity through intelligent control
Data Source
AI summary
A semiconductor device may include a bit line; memory strings connected to the bit line and having different sizes; a sensing node; and a sensing transistor that connects the bit line and the sensing node in response to a sensing signal. In an evaluation period in which the bit line and the sensing node are connected to each other, resistance of a current path between the bit line and the sensing node may be changed according to a size of a selected memory string.