Semiconductor Memory Elements with Rounded Magnetic Edges
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Solution Overview
Problem
The increasing integration density of semiconductor devices leads to technical difficulties such as decreased process margins and increased complexity in unit processes, particularly in forming conductive patterns without the use of a patterning process.
Innovation Solution
The semiconductor device includes lower electrodes with a top width greater than the bottom width, data storage layers with a rounded edge and multiple magnetic layers, an insulating gap-fill layer, and an insulating spacer, all formed without a patterning process, allowing for the separation of conductive patterns and improved fabrication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased, then productivity and device functionality are improved, but process margin decreases and unit process complexity increases
Solution Approach 1:
The patent extracts and eliminates the patterning process from the fabrication sequence. Conductive patterns are formed through direct deposition of conductive material onto the substrate without requiring separate photolithography and etching steps, thereby reducing unit process complexity while maintaining high integration density
Solution Approach 2:
The patent performs preliminary formation of conductive patterns during the deposition process itself rather than requiring subsequent patterning steps. The conductive material is deposited in a controlled manner to directly form the desired patterns, eliminating the need for later pattern transfer operations
2Productivity
If integration density is increased, then productivity is improved, but process margin decreases
Solution Approach 1:
By removing the patterning process entirely, the patent eliminates the cumulative errors that would otherwise accumulate through multiple photolithography and etching steps. This direct deposition approach reduces process variability and improves manufacturing precision while enabling higher integration density
3Manufacturing precision
If patterning process is used to form conductive patterns, then manufacturing precision is maintained, but device complexity and fabrication cost increase
Solution Approach 1:
The patent replaces the mechanical patterning system (photolithography masks, alignment systems, and etching mechanisms) with a direct deposition system. Conductive patterns are formed through controlled material deposition without requiring mechanical pattern transfer, thereby reducing fabrication process complexity while maintaining manufacturing precision
Solution Approach 2:
The patent extracts and removes the entire patterning subsystem from the fabrication process. Conductive patterns are formed directly through deposition control rather than through pattern transfer, eliminating the complexity associated with photolithography, mask alignment, and pattern etching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with separated conductive patterns and memory elements, enhancing integration density while reducing fabrication complexities and costs by eliminating the need for patterning processes.
Implementation Method 1
a data storage layer having a rounded edge and including a plurality of magnetic layers stacked on a top surface of the lower electrode
Data Source
AI summary
Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.