Semiconductor Device Memory Routing for Parallel MAC Processing
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Solution Overview
Problem
Existing semiconductor devices face inefficiencies in processing time due to suboptimal utilization of multiply-accumulate units when performing operations on neural networks, leading to increased processing times.
Innovation Solution
A semiconductor device with a memory having n parallel-accessible banks, multiple multiply-accumulate units, and DMA controllers that distribute pixel data across multiple channels to multiple multiply-accumulate units for parallel processing, and efficiently arrange output data, controlled by a sequence controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If simple commands specifying memory banks are used to control DMA controllers and multiply-accumulate units, then the device is easy to operate, but the multiply-accumulate units are not efficiently utilized leading to increased processing time
Solution Approach 1:
A sequence controller is introduced as an intermediary between the simple command interface and the complex parallel processing operations. The sequence controller automatically generates the necessary control signals to coordinate multiple DMA controllers and multiply-accumulate units based on simple bank allocation commands, enabling efficient parallel processing while maintaining ease of operation through simple command interfaces
Solution Approach 2:
The system dynamically allocates multiple input channels to transfer pixel data from the same input bank to different multiply-accumulate units based on pixel space distribution. This dynamic resource allocation allows the system to adaptively utilize available hardware resources for parallel processing, improving productivity without complicating the command interface
2Device complexity
If pixel data is transferred sequentially through single channels to multiply-accumulate units, then the device complexity is reduced, but the processing time increases due to inability to perform parallel operations
Solution Approach 1:
The pixel data transfer is segmented into multiple parallel channels, each handling different pixel spaces from the same input bank. This segmentation allows simultaneous data transfer to multiple multiply-accumulate units, enabling parallel processing operations while maintaining manageable system complexity through organized channel management
Solution Approach 2:
The system adds a channel dimension to data transfer by using multiple input channels to access the same input bank simultaneously. This dimensional expansion allows parallel data streams to reach different multiply-accumulate units at the same time, transforming sequential processing into parallel processing without excessive complexity
Data Source
AI summary
A second memory has n banks accessible in parallel, and stores pixel data. An input DMA controller respectively transfers the pixel data stored in the second memory to n multiply-accumulate units by using n input channels. A sequence controller controls the input DMA controller so as to cause a first input channel to transfer the pixel data in a first pixel space of the input bank to a first multiply-accumulate unit and cause a second input channel to transfer the pixel data in a second pixel space of the same input bank to a second multiply-accumulate unit.