Semiconductor Memory Row Hammer Control with Fast Count Updates
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAM, face challenges in managing row hammer effects across multiple memory cell rows while maintaining performance and reducing power consumption.
Innovation Solution
The semiconductor memory device incorporates a row hammer management circuit that counts access instances for each memory cell row, performs internal read-update-write operations, and updates count data during a second write time interval smaller than the normal write time interval, all while being controlled by a logic circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory device performs normal write operations to maintain data in all memory cell rows, then data reliability is maintained, but power consumption increases and write time accumulates
Solution Approach 1:
The patent applies local quality by differentiating between count cells and normal memory cells in terms of write operation frequency. Count cells undergo frequent internal write operations to update access counts, while normal memory cells undergo write operations only when data changes are detected. This localized differentiation reduces overall power consumption while maintaining data reliability for both cell types.
Solution Approach 2:
The patent implements partial action by performing write operations on only a subset of memory cells at any given time. Instead of writing to all memory cell rows equally, the system performs internal writes on count cells and external writes on normal cells only when necessary. This partial approach reduces cumulative write time and power consumption while maintaining the required reliability levels.
2Reliability
If the memory device performs frequent write operations to update all memory cell rows, then data freshness is maintained, but write time accumulation increases
Solution Approach 1:
The patent applies partial action by performing write operations on only a subset of memory cells at any given time. Instead of writing to all memory cell rows equally, the system performs internal writes on count cells and external writes on normal cells only when necessary. This partial approach reduces cumulative write time and power consumption while maintaining the required reliability levels.
Solution Approach 2:
The patent implements preliminary action by performing internal write operations on count cells in advance, before external write operations are needed on normal memory cells. This preliminary updating of access counts allows the system to prepare data freshness information proactively, reducing the overall time required for maintaining data freshness across all memory cell rows.
3Reliability
If the memory device implements comprehensive row hammer management for all memory cell rows, then row hammer effects are effectively managed, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing memory cells into two distinct types: count cells dedicated to storing access count information and normal memory cells for data storage. This segmentation allows the row hammer management circuit to handle different cell types with appropriate operations, managing row hammer effects comprehensively while organizing device complexity into manageable, functionally distinct segments.
Solution Approach 2:
The patent implements universality by designing the row hammer management circuit to perform multiple functions: counting access operations, determining row hammer risk, and initiating appropriate write operations. This multi-functional approach consolidates what could be separate complex circuits into a single integrated management unit, effectively managing row hammer across all memory cell rows without proportionally increasing device complexity.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a row hammer management circuit and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The row hammer management circuit counts the number of instances of access of each of the memory cell rows, such as in response to the receipt of an active command, to store the counted values in count cells of each of the memory cell rows as count data and, in response to a first command, initiates an internal read-update-write operation to read the count data, to update the read count data, and to write the updated count data in the count cells. The control logic circuit may performs an internal write operation to write the updated count data in the count cells during a second write time interval that is smaller than a first write time interval associated with a normal write operation.