3D Semiconductor Memory Stack With Segmented Conductive Pattern Formation
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Solution Overview
Problem
The manufacturing process of three-dimensional semiconductor memory devices is complex and requires innovative solutions to simplify the integration of memory cells and conductive patterns, while maintaining device performance.
Innovation Solution
A semiconductor device design featuring alternately stacked interlayer insulating layers and conductive patterns, with channel structures and conductive patterns arranged in a specific configuration to reduce manufacturing complexity, including the use of sacrificial layers and etching processes to form separated conductive patterns and vertical structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in three dimensions on a substrate, then integration density is improved, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming first stack structures with first conductive patterns, then forming second stack structures with second conductive patterns. This segmentation allows each stage to be optimized independently, reducing overall manufacturing complexity while achieving high integration density through vertical stacking
Solution Approach 2:
The patent transitions from planar two-dimensional arrangements to three-dimensional vertical stacking of memory cells. Multiple layers of conductive patterns and insulating layers are stacked in the vertical direction, enabling significantly higher integration density without proportionally increasing manufacturing complexity
2Reliability
If conductive patterns and channel structures are integrated in three dimensions, then device performance is improved, but manufacturing difficulty increases
Solution Approach 1:
The first stack structures with first conductive patterns and first channel structures are formed completely before forming the second stack structures. This preliminary action allows each stacking stage to be completed and verified independently, reducing manufacturing difficulty while maintaining device performance
Solution Approach 2:
Interlayer insulating layers serve as intermediaries between conductive patterns and channel structures, enabling independent formation and integration of these components. The insulating layers facilitate the manufacturing process by providing isolation and structural support during the multi-stage fabrication process
Data Source
AI summary
A semiconductor device, and method of manufacturing a semiconductor device, includes second conductive patterns separated from each other above a first stack structure which is penetrated by first channel structures and enclosing second channel structures coupled to the first channel structures, respectively. Each of the second conductive patterns includes electrode portions stacked in a first direction and at least one connecting portion extending in the first direction to be coupled to the electrode portions.