Semiconductor Memory Devices With Segmented Storage Layers
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing integration density and access times due to uniform memory capacities and array sizes across storage layers, which limits their performance and efficiency.
Innovation Solution
A semiconductor memory device structure with multiple storage layers, where the memory capacity and access time vary based on proximity to the control layer, with smaller capacity and faster access for layers closer to the control layer and larger capacity with slower access for layers farther away, utilizing through-silicon vias for data transmission and different array configurations to optimize data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If uniform memory capacity and array size are used across all storage layers, then manufacturing simplicity is maintained, but integration density and access efficiency are suboptimal
Solution Approach 1:
The memory device is segmented into multiple storage layers (first storage layer, second storage layer, etc.), each with different memory capacities and array configurations. This segmentation allows optimization of integration density by distributing different types of data across layers with appropriate capacities, while maintaining manufacturing feasibility through modular layer structures.
Solution Approach 2:
Different storage layers are assigned different memory capacities and array sizes based on their specific functions. The first storage layer has a first memory capacity with first array size, while the second storage layer has a second memory capacity with second array size. This local differentiation optimizes access efficiency for different data types without requiring complete redesign of the entire memory structure.
2Quantity of substance
If larger array size is used in storage layers, then memory capacity increases, but access time increases
Solution Approach 1:
The patent transitions from a two-dimensional memory organization to a three-dimensional stacked architecture with multiple storage layers. Each layer can be optimized independently for capacity or speed based on its position and function. The first storage layer can be optimized for high capacity with larger arrays, while the second storage layer can be optimized for fast access with smaller arrays, resolving the capacity-speed tradeoff through vertical dimensionality.
Solution Approach 2:
The control layer dynamically selects which storage layer to access based on data requirements. For high-capacity operations, the first storage layer with larger arrays is accessed. For time-critical operations, the second storage layer with smaller arrays is accessed. This dynamic selection allows the system to adapt to different operational requirements without physical reconfiguration.
3Productivity
If multiple storage layers with different capacities are implemented, then access efficiency is optimized, but control complexity increases
Solution Approach 1:
The control layer acts as an intermediary between the external environment and the multiple storage layers. It receives access requests, determines the appropriate storage layer based on data characteristics and access requirements, and routes operations to the correct layer. This intermediary function simplifies the control complexity by centralizing decision-making logic in the control layer rather than requiring distributed intelligence across all storage layers.
Solution Approach 2:
The control layer performs multiple functions: it manages access to both first and second storage layers, handles data routing between layers, and coordinates read/write operations across different array configurations. This multi-functionality consolidates control complexity into a single layer that can be optimized for control logic, rather than distributing complex control requirements across multiple storage layers.
Data Source
AI summary
Semiconductor memory devices include a first storage layer and a second storage layer, each of which includes at least one array, and a control layer for controlling access to the first storage layer and the second storage layer so as to write data to or read data from the array included in the first storage layer or the second storage layer in correspondence to a control signal. A memory capacity of the array included in the first storage layer is different from a memory capacity of the array included in the second storage layer.