3D Semiconductor Memory Device With Segmented Sub-Patterns
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Solution Overview
Problem
The integration density of two-dimensional or planar semiconductor devices is limited by the cost of advanced pattern fineness technologies, necessitating the development of three-dimensional semiconductor memory devices with increased integration and reduced power consumption.
Innovation Solution
A semiconductor memory device with a structure comprising first and second electrodes and a semiconductor pattern, including sequentially disposed sub-semiconductor patterns of different conductivity types, made of transition metal and chalcogen elements, which are interposed between the electrodes and penetrated by an insulating pattern to reduce electron-hole recombination and holding current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked semiconductor patterns. Multiple semiconductor patterns are stacked in the vertical direction (third direction) to increase integration density while maintaining manufacturability through standard semiconductor fabrication processes adapted for 3D structures.
Solution Approach 2:
The semiconductor pattern is divided into multiple sequentially disposed sub-semiconductor patterns (first to fourth sub-semiconductor patterns) with alternating conductivity types. This segmentation creates multiple functional regions within a single vertical stack, enabling higher integration without requiring proportionally more complex manufacturing steps.
2Quantity of substance
If advanced pattern fineness technologies are used to increase integration, then integration density improves, but manufacturing cost increases
Solution Approach 1:
Instead of increasing integration density through finer lateral patterning (which requires expensive advanced lithography), the patent achieves higher integration by stacking semiconductor patterns vertically. This approach uses existing fabrication capabilities in the vertical dimension, avoiding the need for costly cutting-edge pattern fineness technologies.
Solution Approach 2:
Multiple sub-semiconductor patterns with different conductivity types are combined in a single vertical stack structure. This merging of multiple functional elements into one compact 3D unit increases integration density without requiring separate manufacturing processes for each element, thereby controlling manufacturing costs.
3Quantity of substance
If vertically stacked semiconductor patterns are used, then integration density increases, but device complexity increases
Solution Approach 1:
The vertical stack is segmented into sub-semiconductor patterns with alternating conductivity types (n-type and p-type). This regular alternating pattern creates a predictable, systematic structure that, while three-dimensional, follows a simple repeating sequence. Such regularity reduces the complexity of fabrication process control and device operation compared to more irregular 3D configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a highly integrated semiconductor memory device with reduced vertical size and power consumption, achieving higher integration density and efficient operation.
Implementation Method 1
Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element
Data Source
AI summary
A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.