Semiconductor Memory With Segmented Source Lines For Gate Disturb Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor memories, program non-target memory cells connected to the same word line as a program target cell experience gate disturb, leading to changes in threshold voltage, and increasing the source line voltage can improve resistance but also increase current flow through non-target memory cells.

Innovation Solution

A semiconductor memory design where each memory block includes a group of word lines and bit lines intersecting at memory cells connected to a common source line, with separate source lines for programmed and non-programmed blocks, allowing for different voltage supply at program time to minimize gate disturb and leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If voltage of the source line in the block is increased, then the resistance to gate disturb of the program non-target memory cell is improved, but the current which flows through the program non-target memory cell increases

Engineering Contradiction:
Improveresistance to gate disturbVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent divides the memory block into multiple segments, each with its own separate source line. This segmentation allows different voltage levels to be applied to different segments simultaneously, enabling the program segment to operate at lower voltage (reducing leakage current) while non-program segments operate at higher voltage (improving gate disturb resistance).

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different voltage levels to different local regions (segments) of the memory block based on their operational requirements. The program segment receives first voltage optimized for programming with minimal leakage, while non-program segments receive second voltage optimized for gate disturb protection, creating local quality differentiation.

Inventive Principle:
Principle #3Local quality

2Reliability

If voltage of the source line in the block is increased, then the resistance to gate disturb is improved, but the current flow through non-target memory cells increases causing unwanted programming effects

Engineering Contradiction:
Improvegate disturb resistanceVSAvoidgate disturb to non-target cells
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

By segmenting the memory block into multiple independently controllable segments with separate source lines, the patent enables selective voltage application. Only non-program segments receive elevated voltage for gate disturb protection, while the program segment operates at lower voltage, preventing excessive gate disturb from propagating to non-target cells.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The separate source lines act as intermediaries that independently control voltage distribution to different segments. This intermediary structure allows the system to decouple the voltage control for program operations from gate disturb protection, applying each voltage level only where needed and preventing harmful interactions between program and non-program regions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9417818B2Semiconductor memory for capacitively biasing multiple source lines
Publication Date: 2016.08.16 SOCIONEXT INC
  • US9417818B2 patent drawing
  • US9417818B2 patent drawing
  • US9417818B2 patent drawing

AI summary

A memory block area in a semiconductor memory includes program segments. Each program segment includes a group of memory cells arranged at positions where word lines and bit lines intersect and connected to a common source line. The word lines are shared by the program segments. At program operation time source line switches are used for supplying first voltage to a source line in a program segment, of the program segments, including a memory cell to be programmed and supplying second voltage to a source line in a program segment, of the program segments, not including the memory cell to be programmed.