Semiconductor Memory Device Segmented Word Lines
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing power consumption and improving dimensional accuracy due to high power consumption from unselected memory cells in ReRAM technology, which increases production costs and energy usage.
Innovation Solution
The semiconductor memory device incorporates a crosspoint configuration with variable resistance elements and selective elements, using resistance loads to apply specific voltages to unselected wirings, reducing power consumption by minimizing reverse leak current through the use of resistance elements between the power source and unselected wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If ReRAM memory cells are used without MOSFETs to reduce device complexity, then integration density improves, but power consumption from unselected cells increases
Solution Approach 1:
The patent segments the word lines into multiple groups, with each group having its own selection transistor. This segmentation allows independent control of different word line groups, enabling the device to select and activate only specific groups rather than all word lines simultaneously, thereby reducing power consumption from unselected cells while maintaining the simple ReRAM structure
Solution Approach 2:
The patent introduces selection transistors as intermediary elements between the word lines and the memory cells. These transistors act as mediators that control the activation of specific word line groups, preventing direct power consumption from all unselected cells while maintaining the ReRAM memory cell structure without MOSFETs
2Quantity of substance
If finer circuit patterns are used to increase integration density, then memory capacity improves, but lithography process cost increases
Solution Approach 1:
The patent segments the word lines into multiple groups that can be independently controlled. This segmentation allows for more flexible layout designs that can achieve high integration density without requiring excessively fine lithography patterns, as the grouped structure provides additional design freedom in arranging and routing the memory cells
Solution Approach 2:
The selection transistors serve multiple functions: they select specific word line groups for activation, they reduce power consumption by isolating unselected groups, and they enable more flexible layout configurations. This multi-functionality allows the same structural element to contribute to both integration density and manufacturing feasibility
3Speed
If voltage is applied to all word lines simultaneously for memory access, then access speed improves, but power consumption from unselected cells increases
Solution Approach 1:
The patent segments word lines into multiple independently controllable groups. During memory access, only the segment containing the target cell is activated, while other segments remain inactive. This segmentation maintains fast access speed for the selected cell while preventing power consumption and reverse leak current from unselected cells
Solution Approach 2:
The patent applies different voltage states to different segments of word lines based on their selection status. The selected segment receives the appropriate voltage for fast access, while unselected segments are kept at a different voltage level to minimize power consumption. This local differentiation of voltage application reduces reverse leak current without compromising access speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces power consumption across the memory cell array by optimizing voltage application, decreasing the reverse leak current and enhancing operational efficiency without requiring precise alignment, thus lowering production costs and energy usage.
Implementation Method 1
a resistance element having a predetermined resistance value being provided between the power source portion and the unselected first and second wirings
Data Source
AI summary
A semiconductor memory device includes a plurality of first wirings; a plurality of second wirings; a plurality of memory cells positioned at respective intersections of the first wirings and the second wirings, each of the memory cells having a variable resistance element and a selective element connected to the variable resistance element in series; a first selection portion selecting the first wiring; a second selection portion selecting the second wiring; and a power source portion applying predetermined selected-wiring-voltages to a selected first wiring being selected by the first selection portion and a selected second wiring being selected by the second selection portion, respectively, and applying predetermined unselected-wiring-voltages to unselected first wirings other than the selected first wiring and unselected second wirings other than the selected second wiring, respectively. A resistance element having a predetermined resistance value is provided between the power source portion and the unselected first and second wirings.