Semiconductor Memory Independent Selection Gate Voltage Control
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in improving reliability and cost-effectiveness, particularly in three-dimensional stacked flash memory designs where independent control of selection gate lines is complex, leading to issues with data reading and storage reliability.
Innovation Solution
The implementation of a semiconductor memory design with independent voltage control for common and source side selection gate lines, using multiple voltage generation circuits and switch circuits to manage voltages applied to selection gate lines, ensuring reliable data reading and writing by isolating non-selected cells and reducing resistance between the source line and substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent control of selection gate lines is implemented in stacked flash memory, then data reading and writing reliability is improved, but device complexity increases
Solution Approach 1:
The selection gate lines are divided into multiple independent groups (first selection gate lines and second selection gate lines), each controlled by separate voltage generation circuits. This segmentation allows independent control of different cell regions, improving reliability by enabling selective access while reducing control complexity through modular voltage management.
Solution Approach 2:
Switch circuits are introduced as intermediary components between the voltage generation circuits and the selection gate lines. These switch circuits simplify the control architecture by providing a unified control interface that can selectively connect different voltage generation circuits to different gate line groups, thereby reducing overall control complexity while maintaining independent control capability.
2Reliability
If multiple voltage generation circuits are used for independent control, then data reading reliability is improved by reducing disturbance in non-selected cells, but device complexity increases
Solution Approach 1:
The voltage generation system is segmented into multiple independent voltage generation circuits, each responsible for generating voltages for specific selection gate line groups. This allows precise voltage control for selected cells while maintaining appropriate voltage levels for non-selected cells, thereby reducing disturbance and improving reading reliability without requiring complex centralized control.
Solution Approach 2:
Switch circuits serve as intermediaries that simplify the connection between multiple voltage generation circuits and selection gate lines. By providing a standardized switching interface, these circuits reduce the complexity of coordinating multiple voltage generation circuits while enabling independent voltage control for different cell regions.
3Productivity
If resistance between source line and substrate is reduced, then memory performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The connection between the source line and substrate is extended in the vertical dimension by forming a doped region that penetrates through the substrate thickness. This vertical extension increases the effective connection area and length, thereby reducing resistance without requiring higher lateral manufacturing precision.
Solution Approach 2:
The electrical properties of the substrate region are modified by forming a doped region with different conductivity characteristics. By changing the doping concentration and distribution in the vertical direction, the resistance of the source line-substrate connection is reduced while using standard manufacturing processes, avoiding the need for increased manufacturing precision.
Data Source
AI summary
A semiconductor memory includes a first selection transistor and a second selection transistor on one end of a memory string. The first selection transistor includes a channel region in a semiconductor substrate, a channel region in a semiconductor pillar, and a gate electrode connected to a first line. The second selection transistor includes a channel region in the semiconductor pillar and a gate electrode connected to a second line. The first line is connected to a first voltage circuit, and the second line is connected to a second voltage circuit.