Semiconductor Memory Selector for RMW Operation Reduction
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Solution Overview
Problem
Existing semiconductor devices face inefficiencies in RMW operations due to the need for frequent page rewrites, especially when data alignment is not page-based, leading to increased operational time and storage challenges.
Innovation Solution
A semiconductor device with a memory selector that chooses between a NAND memory cell array and a PCRAM cell array based on data alignment, using an address map table to manage sector-based storage and migrate data from the PCRAM array to the NAND array when storage is scarce, thereby reducing the number of RMW operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in a NAND flash memory device on a page basis, then storage capacity is improved, but the number of RMW operations increases when data alignment is not page-based
Solution Approach 1:
The invention segments the storage system into two distinct memory cell arrays: a first memory cell array that stores data according to a first address on a first basis (page-based), and a second memory cell array that stores data according to a second address on a second basis (sector-based). This segmentation allows the system to handle different data alignment requirements separately, reducing the need for RMW operations when data is not page-aligned.
Solution Approach 2:
The invention introduces an address map table as an intermediary component that stores mapping information between the first and second addresses. This address map table acts as a mediator that translates between page-based addresses and sector-based addresses, enabling the system to efficiently manage data storage and retrieval without requiring frequent RMW operations.
2Productivity
If a second memory cell array is added to store sector-based data, then RMW operations are reduced, but device complexity increases
Solution Approach 1:
The memory selector component provides multi-functionality by being able to select between the first memory cell array and the second memory cell array based on the write request characteristics. This universal selector component manages the complexity of having two memory arrays by providing a unified interface for data storage operations.
Solution Approach 2:
The address map table is pre-configured with mapping information between first addresses and second addresses before data storage operations begin. This preliminary preparation of address mappings allows the system to quickly determine which memory array to use without adding complexity to the data storage process itself.
3Productivity
If PCRAM cell array is used for sector-based storage, then data alignment efficiency is improved, but storage management complexity increases when migration is needed
Solution Approach 1:
The memory selector uses feedback from the write request characteristics and address map table to determine whether to select the first or second memory cell array. This feedback mechanism allows the system to dynamically adapt to different storage scenarios and manage the complexity of having two memory arrays with different basis.
Data Source
AI summary
A semiconductor device may include a first memory cell array configured to store data according to a first address on a first basis, a second memory cell array configured to store data according to a second address on a second basis that is relatively smaller than the first basis, a memory selector configured to select one of the first memory cell array and the second memory cell array to store data during a write request, and an address map table configured to store mapping information between the first and second addresses for data stored in the second memory cell array.