Semiconductor Memory Device Self-Aligned Contact Formation
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Solution Overview
Problem
Current semiconductor memory device manufacturing methods are costly and prone to positional shifting between terraces and contacts, requiring multiple lithography processes and increasing the risk of misalignment.
Innovation Solution
A method involving the formation of a stacked body with a stairstep configuration and contacts of varying diameters, where the end portion of the stacked body is patterned simultaneously with contact hole formation, using a hard mask with differently sized holes and a mask material to reduce the number of lithography processes and ensure self-alignment of terraces and contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithography processes are used to form terraces and contacts separately, then positioning precision can be improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the formation of terraces and contacts into a single lithography process. By forming both structures simultaneously using one lithography step, the need for multiple separate lithography processes is eliminated, thereby reducing manufacturing complexity while maintaining positioning precision through the integrated patterning approach.
Solution Approach 2:
The single lithography process serves multiple functions: it simultaneously patterns both the terraces and the contact holes. This multi-functional approach allows one process step to achieve what previously required multiple separate steps, reducing overall manufacturing complexity while ensuring proper alignment between terraces and contacts.
2Manufacturing precision
If multiple lithography processes are used to form terraces and contacts separately, then manufacturing precision can be improved, but manufacturing time increases
Solution Approach 1:
The patent merges the terrace formation and contact hole formation into a single lithography process step. This consolidation eliminates the sequential execution of multiple lithography processes, thereby reducing total manufacturing time while maintaining positioning precision through the simultaneous patterning of both structures.
Solution Approach 2:
The integrated lithography process enables continuous useful action by performing both terrace and contact patterning in one uninterrupted step. This eliminates idle time between separate lithography processes and ensures continuous productive operation, reducing overall manufacturing time while maintaining precision.
3Manufacturing precision
If multiple lithography processes are used, then positioning precision can be improved, but manufacturing cost increases
Solution Approach 1:
The patent combines terrace and contact formation into a single lithography process, eliminating the need for multiple separate lithography steps. This reduction in process count directly lowers manufacturing costs associated with equipment usage, material consumption, and process control, while maintaining positioning precision through the integrated patterning approach.
Solution Approach 2:
The patent eliminates redundant lithography processes that were previously necessary for separate terrace and contact formation. By discarding these unnecessary additional steps and recovering the efficiency gains, the manufacturing cost is reduced while positioning precision is maintained through the optimized single-process approach.
4Manufacturing precision
If separate lithography processes are used for terraces and contacts, then manufacturing precision can be improved, but the number of manufacturing steps increases
Solution Approach 1:
The patent merges the separate lithography processes for terrace and contact formation into a single integrated process step. This consolidation reduces the total number of manufacturing steps while maintaining positioning precision through the simultaneous patterning of both structures in one lithography exposure and development sequence.
Data Source
AI summary
According to one embodiment, a method for manufacturing a semiconductor memory device includes: forming a stacked body including insulating films stacked alternately with electrode films, a memory hole is made in one portion of the stacked body to extend in a stacking direction, a charge storage layer is provided on an inner surface of the memory hole, a semiconductor member is provided in the memory hole; forming a hard mask on the stacked body, the hard mask has a plurality of holes of mutually different sizes; plugging the smallest of the holes while shrinking the other holes by depositing a mask material; making contact holes by removing a prescribed number of the insulating films and a prescribed number of the electrode films in regions directly under the other holes by performing etching using the mask material and the hard mask as a mask; and filling conductive material into the contact holes.