Semiconductor Memory Device Shared CG Driver Multi-Plane Read
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently reading data from multiple planes with different data levels simultaneously, leading to increased complexity and reduced read speed due to the need for precise voltage applications and control signals.
Innovation Solution
The semiconductor memory device employs a configuration with shared CG drivers for word lines across planes, allowing for simultaneous multi-plane read operations by applying specific read voltages to selected word lines and controlling the control signal STB for each plane to read only necessary data, while using SL drivers to adjust source line voltages for varying threshold levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate CG drivers are used for each plane to enable simultaneous multi-plane read operations, then read speed is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple CG drivers into a single shared CG driver that serves multiple planes. The shared driver applies different read voltages to word lines of different planes by controlling the potential difference between CG lines and SL lines, eliminating the need for separate CG drivers per plane while maintaining simultaneous multi-plane read capability
Solution Approach 2:
The patent changes the voltage parameters dynamically by applying different potentials to CG lines and SL lines. By adjusting the potential difference between CG and SL lines, the shared CG driver can provide different read voltages (e.g., first read voltage for first plane, second read voltage for second plane) to different planes during simultaneous read operations
2Productivity
If multiple read voltages are applied to different planes simultaneously, then read efficiency is improved, but control complexity increases
Solution Approach 1:
The patent introduces SL lines as intermediary elements between the shared CG driver and the memory planes. The SL lines act as mediators that, when combined with CG lines, enable the shared driver to provide different read voltages to different planes without requiring separate control circuits for each plane
Solution Approach 2:
The shared CG driver performs multiple functions by serving different planes with different read voltages simultaneously. The same CG driver circuitry is used to apply first read voltage to first plane and second read voltage to second plane, making the driver universal across multiple planes
3Measurement precision
If precise voltage control is implemented for each plane, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple voltage control functions into a single shared CG driver that precisely controls voltages for multiple planes. By combining the drivers while maintaining precise voltage control through CG and SL line potential management, the system achieves accurate voltage application without proportional increase in control circuit complexity
Data Source
AI summary
A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.