Semiconductor Memory Device With Shared Diffusion Lines
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Solution Overview
Problem
The scaling of Integrated Circuits (ICs) has led to performance and functionality gains, but memory technology has stalled, with wire degradation and high energy costs in memory fetches, necessitating innovative approaches to increase memory capacity and performance without increasing production costs.
Innovation Solution
The development of a semiconductor device with a new NOR architecture that utilizes shared source and drain diffusion lines, junction-less transistors, and monocrystalline channels, allowing for high-speed access and high-density memory storage through a 3D transistor structure with independent storage sites and advanced charge trapping mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If component sizes are reduced through scaling, then transistor performance and density improve, but wire performance degrades and wire lengths increase
Solution Approach 1:
The patent transitions from planar 2D transistor layout to three-dimensional FinFET structures, enabling vertical channel formation that reduces wire lengths while maintaining transistor density. The FinFET architecture allows current flow through vertical fins, effectively utilizing the third dimension to overcome wire degradation issues associated with continued scaling.
2Quantity of substance
If memory capacity is increased through traditional scaling, then production costs increase, but capacity needs to continue growing
Solution Approach 1:
The patent employs three-dimensional stacked memory architectures with multiple memory layers stacked vertically, increasing memory capacity without proportionally increasing chip area or production complexity. This vertical stacking approach allows higher density storage while maintaining cost-effective manufacturing processes.
Solution Approach 2:
The patent implements shared source and drain diffusion lines that serve multiple memory cells simultaneously, reducing the number of separate components needed and thereby lowering production costs while maintaining high memory capacity.
3Use of energy by moving object
If wire lengths are reduced through 3D stacking, then energy consumption decreases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory structure into discrete stacked layers with standardized interconnect patterns, allowing modular manufacturing that reduces overall complexity despite the three-dimensional architecture. Each layer can be processed independently using similar fabrication techniques.
Solution Approach 2:
The patent utilizes shared source and drain diffusion lines that serve multiple functions across different memory cells and layers, simplifying the interconnect structure and reducing manufacturing complexity while achieving short wire lengths and low energy consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient memory storage with reduced wire lengths, lower construction costs, and enhanced performance by leveraging shared diffusion lines and advanced charge trapping techniques, addressing the limitations of traditional memory technologies.
Implementation Method 1
a first memory cell comprises a thin tunneling oxide of less than 1 nm thickness
Implementation Method 2
a second memory cell comprises a thick tunneling oxide of greater than 2 nm thickness
Data Source
AI summary
A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where the first memory cell includes a thin tunneling oxide of less than 1 nm thickness, and where the second memory cell includes a thick tunneling oxide of greater than 2 nm thickness.