Semiconductor Memory Device With Shared Word Line Drivers
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration and cost reduction while maintaining effective voltage-current characteristics and write operation efficiency, particularly in three-dimensional stacked memory cell arrays.
Innovation Solution
The semiconductor memory device incorporates a circuit configuration with a stacked structure of memory cells, utilizing resistance change elements and selector elements in specific arrangements to facilitate common manufacturing methods and conform physical properties across layers, along with optimized arrangements of word line and bit line drivers to reduce chip size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked into a three-dimensional structure to achieve high integration, then integration density is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple memory cell layers (first memory cell layer, second memory cell layer, etc.) stacked in the third direction. Each layer contains memory cells formed between corresponding word lines and bit lines, allowing independent addressing and operation. This segmentation enables high integration density while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The patent transitions from a two-dimensional planar memory structure to a three-dimensional stacked structure by forming multiple memory cell layers in the vertical direction (third direction). This dimensional change increases storage capacity per chip area while the patent manages the resulting complexity through shared driver circuits and systematic addressing schemes.
2Reliability
If driver circuits are duplicated for each memory cell layer to maintain effective voltage-current characteristics, then electrical performance is improved, but chip size increases
Solution Approach 1:
Adjacent memory cell layers share common driver circuits (first driver, second driver, third driver) that can be collectively controlled. The first driver controls word lines across multiple layers, the second driver controls bit lines, and the third driver controls select lines. This merging of driver functions reduces the total number of drivers needed compared to having dedicated drivers for each layer, thereby reducing chip size while maintaining effective voltage-current characteristics through coordinated control.
Solution Approach 2:
The driver circuits are designed with multi-functional capability to serve multiple memory cell layers simultaneously. The first driver can apply voltages to word lines in different layers, the second driver controls bit lines across layers, and the third driver manages select lines for layer selection. This universality allows a reduced set of drivers to effectively control the entire stacked memory structure without sacrificing electrical performance.
3Adaptability or versatility
If more driver circuits are added to control additional memory cell layers, then functionality is improved, but power consumption increases
Solution Approach 1:
Multiple memory cell layers share common driver circuits that can be collectively controlled through the third driver which manages select lines. This merging reduces the total number of independently operated drivers, thereby reducing overall power consumption while maintaining the functionality to address and operate on multiple layers through coordinated control signals.
Solution Approach 2:
The third driver controls select lines to periodically activate specific memory cell layers for read or write operations. By enabling only the required layer at any given time rather than continuously powering all layers, the system achieves periodic action that reduces average power consumption while maintaining full functionality across all layers when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables reduced chip size, improved integration, and efficient voltage-current characteristics, while minimizing power consumption during write and read operations by sharing drivers between adjacent memory cell layers.
Implementation Method 1
Memory cells included in a ReRAM have resistance change layers in which resistance values change upon application of a voltage
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes the following configuration. First Lower word line drivers are arranged between adjacent mats, and first upper word line drivers are arranged between the first Lower word line drivers. Second Lower word line drivers are arranged between another adjacent mats, and second upper word line drivers are arranged between the second lower word line drivers. The first and second upper word line drivers are shared by the adjacent mats respectively.