Semiconductor Memory Device Shared Predecode Signal Architecture
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Solution Overview
Problem
In semiconductor memory devices with banks arranged at the ends of a chip, the long data buses between pad electrode regions lead to decreased data transfer speed and increased wire pitch, along with a small operating margin due to address latching delays.
Innovation Solution
Implementing a semiconductor memory device with address through predecoders that share predecode signals between banks, eliminating the need for individual address latching in each bank and reducing the number of predecode signal wires, while using main and sub-word control circuits to manage select signals for each bank.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pad electrode regions are arranged at ends of the chip, then data I/O width can be increased, but data bus length increases and data transfer speed decreases
Solution Approach 1:
The memory device is divided into multiple banks (#0, #1, #2, #3) that can be independently operated. Each bank has its own data I/O path to the pad electrode regions, allowing parallel data transfers and reducing the effective bus length for each data path.
Solution Approach 2:
The patent introduces a bank dimension to the data path architecture. Instead of a single long data bus from one end of the chip to the other, data can be accessed through multiple shorter paths via different banks, effectively adding a spatial dimension to data routing.
2Productivity
If individual address latching is implemented in each bank, then parallel bank operation is enabled, but operating margin decreases due to latch delays
Solution Approach 1:
The address latching function is merged into a shared row address latch circuit that serves all banks. The latch output is then distributed to all banks simultaneously, eliminating the need for separate latch circuits in each bank and reducing the overall delay.
Solution Approach 2:
The row address latch circuit is designed as a universal component that can serve multiple banks simultaneously. Its output is distributed to all banks through common signal lines, allowing the same latching mechanism to support parallel operation across all banks without requiring bank-specific customization.
3Speed
If banks are positioned in an aligning manner between pad electrode regions, then data bus length is reduced, but the number of predecode signal wires increases
Solution Approach 1:
Multiple predecode signal lines that would otherwise need to be routed to each bank individually are merged into shared signal paths. The row address latch output and predecoder outputs are distributed through common lines that serve multiple banks, reducing the total wire count while maintaining proper signal distribution.
Solution Approach 2:
The patent reorganizes the signal distribution architecture by introducing a hierarchical dimension. Instead of direct point-to-point connections between each predecoder and each bank, signals are distributed through intermediate stages that serve multiple banks, effectively reducing the wiring complexity.
Data Source
AI summary
A semiconductor memory device includes a plurality of banks #0 to #3, a predecoder that generates a predecode signal, first latch circuits, each of which is assigned to the banks, that hold a first portion of the predecode signal, a main decoder that is assigned in common to the two banks, and receives a second portion of the predecode signal and outputs of the first latch circuits. The main decoder includes latch circuits that hold by each bank a decoded signal obtained by decoding the second portion of the predecode signal. In the present invention, an address through predecoder is used to latch a predecode signal, and hence it becomes possible to share one portion of the predecode signal between the banks.