Semiconductor Memory Signal Level Control for Capacity Integration
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Solution Overview
Problem
Current semiconductor memory systems face challenges in increasing capacity while maintaining integration degree, leading to increased time and manufacturing costs, and unnecessary current consumption when multiple chips are integrated, as they require redesign and additional control circuits for address signals.
Innovation Solution
A semiconductor memory apparatus with a signal level control unit that adjusts command and address signals to control chip operations, allowing for various capacities and structures using existing designs, including a buffer section and control signal setting unit to manage signal levels and activate necessary signals based on desired configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two semiconductor chips are stacked to increase capacity, then the capacity of the semiconductor memory apparatus increases, but the integration degree of the memory system decreases
Solution Approach 1:
The patent applies dynamics by making the memory system configurable through control signals. The memory apparatus can dynamically switch between different operating modes (SDP mode with one chip active, DDP mode with two chips active) based on control signals from the memory controller. This allows the system to adapt its capacity and integration characteristics dynamically rather than being fixed by the physical stacking configuration.
Solution Approach 2:
The patent implements universality by designing the memory apparatus to serve multiple functions through a single physical configuration. The stacked semiconductor chips are designed to operate in different capacities (4Gb, 8Gb, 16Gb) depending on the control signals received. This multi-functionality eliminates the need for separate memory apparatus designs for different capacities, resolving the contradiction between capacity and integration degree.
2Device complexity
If one semiconductor chip with 8Gb capacity is used, then the integration degree of the memory system improves, but additional address buffers and control circuits are required, increasing the size of the memory system
Solution Approach 1:
The patent applies partial action by activating only the necessary semiconductor chips and control circuits based on the desired capacity. When operating in 4Gb mode, only one chip and its associated control circuits are activated, while the other chip and its control circuits remain inactive. This partial activation reduces the effective size of the memory system while maintaining the physical integration benefits of the stacked configuration.
3Quantity of substance
If multiple semiconductor chips are integrated, then the capacity increases, but unnecessary current is consumed when not all chips are needed
Solution Approach 1:
The patent implements periodic action through the sequential or selective activation of semiconductor chips based on control signals. The memory controller selectively activates specific chips based on the desired capacity configuration, rather than continuously powering all chips. This selective activation pattern reduces unnecessary current consumption while maintaining the capability to access higher capacity when needed.
Solution Approach 2:
The patent applies self-service by enabling the memory apparatus to automatically configure its own operation based on control signals. The memory controller sends control signals that automatically enable or disable specific chips and adjust address buffer operations without requiring manual intervention. This self-configuring capability ensures optimal power consumption by activating only the necessary chips for the current operational mode.
4Device complexity
If the memory system is redesigned to satisfy integration degree requirements, then the integration degree improves, but time and manufacturing cost increase
Solution Approach 1:
The patent applies preliminary action by pre-configuring the stacked semiconductor chips with the capability to operate in multiple modes during the manufacturing process. The physical stacking and basic circuitry are prepared in advance, but the final configuration is determined by control signals at operation time. This preliminary preparation eliminates the need for complete redesign when different capacity configurations are needed, reducing design time while maintaining integration degree benefits.
Data Source
AI summary
A semiconductor memory apparatus includes one or more semiconductor chips configured to have predetermined capacity and structure; and a signal level control unit configured to control levels of external signals, which are input to the one or more semiconductor chips, in order to realize various capacities and structures using the one or more semiconductor chips.