Semiconductor Memory Device Simultaneous Word Line Activation
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Solution Overview
Problem
Conventional semiconductor memory devices reduce data availability and operation efficiency due to the need to activate one word line at a time, leading to increased time intervals between read/write operations.
Innovation Solution
A semiconductor memory device that activates multiple memory cell blocks and word lines simultaneously, using a column decoding block to sequentially access and input/output data by decoding column and row addresses, allowing continuous read/write operations without separate active commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one word line is activated at a time, then stable operation is maintained, but data availability decreases and operation efficiency reduces
Solution Approach 1:
The memory bank is divided into multiple memory cell blocks (first memory cell block, second memory cell block, etc.), each capable of independent activation. This segmentation allows multiple blocks to be activated simultaneously without interfering with each other, enabling parallel data operations while maintaining stability within each block.
Solution Approach 2:
The system dynamically activates different memory cell blocks based on read/write commands. When a read command is received, the system activates appropriate blocks and sequentially selects bit lines for data output. When a write command is received, the system activates blocks and sequentially selects bit lines for data input. This dynamic activation strategy maximizes data availability while maintaining operational stability.
2Reliability
If one word line is activated at a time, then operation stability is maintained, but time interval between operations increases
Solution Approach 1:
The system performs preliminary activation of multiple memory cell blocks before actual read/write operations. By activating blocks in advance and maintaining them in an active state, the system eliminates waiting time between operations. The column decoding unit can then immediately proceed with bit line selection and data transfer without requiring reactivation of word lines.
Solution Approach 2:
The system maintains continuous useful action by keeping multiple memory cell blocks activated simultaneously and sequentially selecting bit lines for data operations. This continuous operation eliminates idle time between read/write commands, as the system can immediately transition from one block to another without deactivating and reactivating word lines, thereby reducing the time interval between operations.
3Productivity
If multiple memory cell blocks are activated simultaneously, then data availability increases, but device complexity increases
Solution Approach 1:
The word line activation unit is designed with multi-functionality to handle multiple memory cell blocks. It can activate different blocks based on read/write commands and sequentially select bit lines within activated blocks. This universal design allows the same activation unit to manage multiple blocks without requiring separate control circuits for each block, thereby managing complexity while enabling simultaneous activation.
Solution Approach 2:
The column decoding unit acts as an intermediary between the address inputs and the memory cell blocks. It decodes column addresses and coordinates with the word line activation unit to selectively activate appropriate blocks and bit lines. This intermediary function simplifies the overall control complexity by centralizing the coordination of multiple block activations and data operations through a single decoding and control mechanism.
4Speed
If multiple word lines are activated simultaneously, then data input/output speed improves, but potential difference detection becomes more complex
Solution Approach 1:
The bit line structure is segmented into multiple independent bit line pairs, with each pair serving a specific memory cell block. The sense amplifier is configured to detect potential differences in each bit line pair independently. This segmentation allows simultaneous data operations across multiple blocks without interfering with the detection process, maintaining speed while managing complexity through independent detection channels.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cell blocks each including a plurality of word lines and suitable for being selectively activated based on an active command and a row address, wherein word lines are selected from the respective activated memory cell blocks based on the active command and the row address, and a column decoding block sequentially accessing the activated memory cell blocks to input/output data thereof by decoding a column address based on the row address.