3D Semiconductor Memory Device Slit Spacing Optimization
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Solution Overview
Problem
The integration of semiconductor memory devices is limited by the complexity and cost of fine pattern formation in two-dimensional structures, necessitating the development of three-dimensional structures to enhance performance and reduce costs.
Innovation Solution
A semiconductor memory device with a three-dimensional structure featuring a stack with alternating dielectric and electrode layers, where the distance between slits in the connection area is greater than in the cell area, allowing for selective etching and formation of electrode layers, thereby increasing integration density without additional manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a two-dimensional planar semiconductor memory device is used, then the structure is simple and manufacturing is easier, but the degree of integration is limited due to the area occupied by unit memory cells
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by stacking multiple electrode layers and dielectric layers vertically. This dimensional change allows memory cells to be arranged in three dimensions rather than confined to a plane, significantly increasing the degree of integration without proportionally increasing the occupied area
2Quantity of substance
If a three-dimensional structure with alternating dielectric and electrode layers is implemented, then the integration density increases, but the manufacturing process complexity increases due to selective etching requirements
Solution Approach 1:
The patent applies local quality by having different dielectric layers (first and second dielectric layers) with distinct properties in different regions. The second dielectric layer has different etching characteristics that allow selective removal in the connection area while preserving it in the cell area, enabling region-specific manufacturing operations
Solution Approach 2:
The patent segments the stack into distinct regions (cell area and connection area) with different structural characteristics. The connection area has a different configuration of dielectric layers compared to the cell area, allowing independent processing and optimization of each region
3Ease of manufacture
If the distance between slits in the connection area is made larger than in the cell area, then selective etching is enabled, but the structural uniformity is reduced
Solution Approach 1:
The patent implements local quality by creating different slit spacing configurations in different areas. The cell area maintains smaller, uniform slit spacing for high-density memory cells, while the connection area has larger slit spacing to accommodate connection structures, allowing each region to be optimized for its specific function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances integration density and reduces manufacturing costs by simplifying the process, minimizing process failures, and allowing for more efficient use of the cell area, while maintaining the integrity of the connection area.
Implementation Method 1
removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits
Data Source
AI summary
A method for manufacturing a semiconductor memory device may include: forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area; forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area; removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits; and forming electrode layers in spaces from which the second dielectric layers are removed.