Semiconductor Memory Spacer Capping Pattern for Parasitic Capacitance Reduction
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Solution Overview
Problem
The challenge in semiconductor memory devices is to achieve dense integration while maintaining excellent reliability, as emerging exposure techniques and equipment are expensive and inefficient.
Innovation Solution
The solution involves a semiconductor memory device design with a first and second impurity region, a bit line connected to the first impurity region, a storage node contact connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad connected to the storage node contact, a buried dielectric pattern on the sidewall of the landing pad and air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap, which allows for dense integration and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If line pattern widths are reduced to facilitate denser integration, then integration density is improved, but manufacturing precision and reliability deteriorate due to limitations in emerging exposure techniques
Solution Approach 1:
The patent segments the structure by introducing an air gap that divides the space between the bit line and storage node contact into distinct regions. This segmentation allows the bit line and storage node contact to be positioned closer together while maintaining electrical isolation, thereby achieving higher integration density without compromising manufacturing precision
Solution Approach 2:
The patent introduces an air gap as an intermediary element between the bit line and storage node contact. This air gap acts as a mediator that enables closer spacing of conductive elements while maintaining reliable electrical isolation, resolving the contradiction between integration density and manufacturing precision
2Reliability
If conventional fabrication techniques are used, then manufacturing reliability is maintained, but fabrication cost increases due to expensive emerging exposure techniques and equipment
Solution Approach 1:
The patent employs a sacrificial spacer that is intentionally designed to be temporary and removable. This sacrificial spacer enables the formation of the air gap using conventional, cost-effective fabrication techniques rather than expensive emerging exposure techniques, thereby reducing fabrication cost while maintaining reliability
Solution Approach 2:
The patent changes the physical state and properties of materials during fabrication by using thermal decomposition to convert the sacrificial spacer into a removable form. This parameter change enables the creation of the air gap structure using standard fabrication processes, avoiding the need for expensive specialized equipment
3Ease of manufacture
If dielectric pattern is formed on lateral surfaces during fabrication, then manufacturing process is simplified, but device reliability deteriorates due to increased parasitic capacitance
Solution Approach 1:
The patent extracts or removes the dielectric material from the region between the bit line and storage node contact by creating an air gap. This extraction eliminates the source of parasitic capacitance that would otherwise be present if dielectric pattern were formed on lateral surfaces, thereby improving device reliability while maintaining fabrication simplicity through the sacrificial spacer approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables dense integration of semiconductor memory devices with enhanced reliability by reducing parasitic capacitance and improving the distribution of parasitic capacitance between the bit line and storage node contact, while also preventing dielectric pattern formation on lateral surfaces, thus reducing fabrication costs.
Implementation Method 1
forming a thermal decomposition layer that fills the air gap and the recession
Data Source
AI summary
A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.