Semiconductor Memory Stacked Chip Interlocking
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration density and operational reliability, particularly in three-dimensional designs, which affect their portability and capacity.
Innovation Solution
The semiconductor memory device incorporates a stacked structure with alternately arranged conductive and insulating patterns, featuring protrusions and recesses on the bonding surfaces of chips to enhance bonding strength and durability, thereby improving integration density and operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional stacked structure is adopted to increase integration density, then integration density is improved, but bonding reliability between chips deteriorates
Solution Approach 1:
The patent implements protrusions extending from one chip into recesses of the other chip, creating a nested interlocking structure. The protrusions from the first chip fit into recesses of the second chip, and vice versa, forming a mechanically interlocked bonded interface that enhances bonding reliability while maintaining high integration density through the three-dimensional stacked configuration.
Solution Approach 2:
The protrusions and recesses create a mechanically interlocking interface that distributes stress more evenly across the bonding area. The curved or rounded contours of the protrusions fitting into recesses reduce stress concentration points compared to flat bonding surfaces, thereby improving bonding reliability in the three-dimensional stacked structure.
2Quantity of substance
If chip stacking is increased to improve integration density, then capacity is improved, but operational reliability deteriorates
Solution Approach 1:
The nested interlocking structure of protrusions and recesses provides mechanical stability to the stacked chips, ensuring that increased capacity through additional stacking does not compromise operational reliability. The interlocking geometry maintains precise alignment and reduces the risk of delamination or displacement under operational stress.
Solution Approach 2:
The protrusions and recesses are designed to absorb and distribute mechanical stresses before they can propagate through the bonded interface. This pre-engineered stress distribution mechanism cushiones the bonded chips against thermal expansion, contraction, and external forces, maintaining operational reliability as the number of stacked chips increases for higher capacity.
3Volume of moving object
If bonding surface area is reduced for portability, then device size is improved, but bonding strength deteriorates
Solution Approach 1:
The protrusions extending into recesses create a three-dimensional interlocking structure that increases the effective bonding interface volume without increasing the planar footprint. This nested configuration provides enhanced mechanical strength and resistance to shear forces while maintaining a compact device size suitable for portable applications.
Solution Approach 2:
The patent transitions from a two-dimensional flat bonding interface to a three-dimensional interlocking structure by extending protrusions into recesses in the vertical dimension. This dimensional transformation increases bonding strength through volumetric interlocking while keeping the device's planar dimensions small for portability.
Data Source
AI summary
A semiconductor memory device includes a first chip having a peripheral transistor and a first insulating layer, and includes a second chip having a stacked structure and a second insulating layer. The stacked structure includes conductive patterns and insulating patterns alternately stacked with each other, the first insulating layer includes a first bonding surface, the second insulating layer includes a second bonding surface contacting the first bonding surface, and the second chip further includes a protrusion protruding from the second bonding surface of the second insulating layer toward the first insulating layer.