Semiconductor Memory Device Stacked Structure Etching Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor memory devices, particularly those with cross-point cell structures, faces challenges in achieving accurate wiring structures without short-circuits, which increases production costs due to the complexity of lithography techniques and the need for precise size and position accuracy.
Innovation Solution
A method of manufacturing semiconductor memory devices involves forming stacked structures with alternating etching patterns to create stripe and hook parts in bit and word lines, ensuring accurate alignment and contact formation without material remnants that could cause short-circuits, using a repetitive process to stack and etch layers into matrix patterns, and forming contact plugs that extend perpendicular to the etched directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography techniques are used to form patterns for miniaturized semiconductor memory devices, then the size accuracy and position accuracy of patterns can be improved, but the production cost increases due to the complexity of lithography techniques
Solution Approach 1:
The patent divides the memory cell structure into stacked layers with alternating conductive and insulating layers. Each layer is formed using simpler lithography techniques, and the three-dimensional cross-point structure is achieved through vertical stacking rather than complex planar patterning. This segmentation into manageable layers reduces the complexity of individual lithography steps while maintaining high precision through cumulative layer alignment.
Solution Approach 2:
The patent transitions from conventional two-dimensional planar memory cell structures to a three-dimensional stacked cross-point architecture. By adding the vertical dimension with multiple stacked layers, the patent achieves higher integration density and more accurate pattern formation using relatively simpler lithography processes for each layer, avoiding the need for extremely complex multi-patterning techniques.
2Productivity
If cross-point cell structure is used to miniaturize memory cells, then the memory cell integration can be improved, but the risk of short-circuit increases due to inaccurate wiring structure formation
Solution Approach 1:
The patent introduces insulating layers as intermediary materials between conductive layers in the stacked structure. These insulating layers act as spacers and barriers that precisely define the separation between adjacent bit lines and word lines, preventing short-circuits while enabling accurate wiring formation. The insulating layers serve as mediators that maintain electrical isolation in the high-density cross-point architecture.
Solution Approach 2:
The patent employs a nested structure where conductive and insulating layers are alternately stacked, with each layer nested within the overall three-dimensional structure. The insulating layers are nested between conductive layers, and the entire stack is nested within the memory device architecture. This nested arrangement ensures precise spatial relationships between wiring elements, preventing short-circuits while maximizing integration density.
3Manufacturing precision
If more lithography steps are used to achieve precise wiring structure, then the wiring accuracy can be improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent employs periodic alternation of conductive and insulating layers in the stacked structure. This periodic stacking pattern allows for systematic and repetitive manufacturing processes, where the same lithography and deposition steps are repeated for each layer pair. The periodic nature of the structure enables standardized manufacturing procedures, improving wiring accuracy through consistent layer formation while maintaining ease of manufacture through process repetition.
Data Source
AI summary
A method of manufacturing a semiconductor memory device according to the embodiment includes: forming a first stacked-structure; forming a first stripe part and a first hook part at the first stacked-structure; forming a second stacked-structure on the first stacked-structure; forming a second stripe part and a second hook part at the second stacked-structure; repeating the above-described four steps for a certain number of times; and forming a contact plug contacting the first or second hook parts. The etching is conducted to remove the first stacked-structure in a region at which the second hook part is to be formed in the second stacked-structure higher than the first stacked-structure by one layer. The etching is conducted to remove the second stacked-structure in a region at which the first hook part is to be formed in the first stacked-structure higher than the second stacked-structure by one layer.