Semiconductor Memory Device Stacked Structure Lateral Etching
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Solution Overview
Problem
As semiconductor memory devices, such as DRAM, shrink in size, it becomes increasingly difficult to fabricate interconnecting structures between memory cells, leading to issues like direct shorting and reduced device reliability due to the challenge of reducing the lateral extent of stacked structures over substrates.
Innovation Solution
A method involving multiple etching processes, including wet etching, is used to form a semiconductor memory device with a stacked structure that covers capacitors, where the lateral portions extending towards peripheral regions are progressively reduced, preventing direct contact with peripheral plugs and enhancing device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the stacked structure is extended to cover the capacitor structure, then the capacitor is protected and electrically isolated, but the lateral portion may directly contact the peripheral plug causing short circuit
Solution Approach 1:
An insulating layer is introduced as an intermediary between the conductive layer and the substrate. This insulating layer extends laterally beyond the capacitor structure to create an electrical barrier that prevents the conductive layer from directly contacting the peripheral plug, thus eliminating the short circuit risk while maintaining the protective coverage of the stacked structure over the capacitor
Solution Approach 2:
The solution transitions from a two-dimensional planar layout concern to a three-dimensional vertical stacking approach. By extending the insulating layer laterally in the horizontal dimension beyond the capacitor footprint, the design creates vertical electrical isolation that prevents contact between the conductive layer above and the peripheral plug on the substrate level, effectively using dimensional extension to solve the interference problem
2Reliability
If the lateral portion of the stacked structure is reduced to prevent shorting, then the risk of direct contact with peripheral plug is minimized, but the process complexity increases due to multiple etching steps
Solution Approach 1:
The manufacturing process is segmented into multiple etching steps: a first etching process that partially removes the insulating layer to expose portions of the conductive layer, and a second etching process that further removes the insulating layer to completely expose the conductive layer. This segmentation allows precise control over the lateral dimensions of the stacked structure, reducing it to the minimum required size to prevent shorting while maintaining manufacturing feasibility through systematic process breakdown
Solution Approach 2:
The insulating layer is first formed to extend laterally beyond the capacitor structure, creating a preliminary protective barrier. Subsequent etching processes then selectively remove portions of this pre-formed insulating layer to achieve the final optimized dimensions. This preliminary action of forming the insulating layer first provides a foundation that simplifies the subsequent patterning and etching steps, as the insulating layer serves as both the protective element and the material to be precisely removed
3Productivity
If the device dimension is shrunk for higher density, then the device density increases, but the fabrication difficulty of interconnecting structure increases
Solution Approach 1:
The invention addresses the fabrication difficulty in miniaturized devices by transitioning to vertical stacking architecture. Instead of relying on complex lateral interconnections in the planar dimension, the design stacks the insulating layer and conductive layer vertically over the capacitor structure, creating vertical interconnections that are easier to fabricate at small dimensions. This vertical dimension approach bypasses the interconnection challenges inherent in highly scaled lateral layouts
Solution Approach 2:
The stacked structure with insulating and conductive layers is applied locally over specific capacitor structures where interconnection is needed. The insulating layer is formed to extend laterally beyond the capacitor to provide localized electrical isolation, and the conductive layer is positioned to provide localized electrical connection. This localized application of the stacked structure allows high device density through selective placement rather than requiring complex global interconnection schemes across the entire device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enlarges the process window for forming plugs, reduces the risk of short circuits, and allows for higher device density and integrity by minimizing the space between memory cell and peripheral regions.
Implementation Method 1
a stacked structure disposed on a capacitor structure is etched by multiple etching processes including a wet etching process
Data Source
AI summary
A method of forming semiconductor memory device, the semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.