3D Semiconductor Memory Stacked Mold Structures Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of semiconductor memory devices is limited by the complexity of forming fine patterns, which restricts the degree of integration and increases costs, while two-dimensional devices face limitations in miniaturization and three-dimensional devices are proposed to enhance performance and reduce prices.
Innovation Solution
A semiconductor memory device with a multi-stack structure, including a cell substrate with extension regions and through regions, and mold structures with gate electrodes and interlayer insulating layers of varying impurity concentrations, allowing for improved channel and contact structures that enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar semiconductor memory devices are used, then the manufacturing process is simpler, but the degree of integration is limited due to area constraints
Solution Approach 1:
The patent transitions from two-dimensional planar memory devices to three-dimensional stacked memory devices by stacking multiple mold structures vertically. This dimensional change allows multiple memory cells to be integrated in the vertical direction, significantly increasing the degree of integration without requiring more complex planar patterning processes.
2Manufacturing precision
If three-dimensional stacked structures are implemented, then the degree of integration increases, but the structural complexity increases
Solution Approach 1:
The patent divides the three-dimensional memory structure into multiple independent mold structures, each containing gate electrodes and interlayer insulating layers. Each mold structure can be formed and processed separately, then stacked together. This segmentation reduces the overall structural complexity by breaking down the complex 3D structure into manageable modular units.
Solution Approach 2:
The patent implements a nested structure where multiple mold structures are stacked vertically, with each mold structure containing nested layers of gate electrodes and interlayer insulating layers. The first mold structure is stacked on the cell substrate, the second mold structure is stacked on the first mold structure, and so on, creating a nested hierarchical arrangement that increases integration while managing complexity through systematic layering.
3Ease of manufacture
If uniform impurity concentration is used in interlayer insulating layers, then the manufacturing process is simpler, but the etching selectivity and reliability are reduced
Solution Approach 1:
The patent applies different impurity concentrations to different interlayer insulating layers based on their specific functional requirements. The first interlayer insulating layer has a first impurity concentration optimized for its etching characteristics, while the second interlayer insulating layer has a second impurity concentration optimized for its etching characteristics. This local quality differentiation improves etching selectivity and overall device reliability without significantly complicating the manufacturing process.
Data Source
AI summary
Semiconductor memory devices may include a cell substrate including a cell array region, first and second extension regions and a through region, a first mold structure including first gate electrodes stacked in a stepwise manner, a first interlayer insulating layer extending conformally on the first gate electrodes on the second extension region, a second interlayer insulating layer on the first interlayer insulating layer, a second mold structure including second gate electrodes on the second interlayer insulating layer and stacked on the first extension region in the stepwise manner, a channel structure in the first and second mold structures on the cell array region, a first cell contact structure in the first mold structure on the second extension region, and a second cell contact structure in the first and second mold structures on the first extension region. The first and second interlayer insulating layers may have different impurity concentrations.