Semiconductor Memory Stepped Stacking for Pad Area
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Solution Overview
Problem
As semiconductor memory cards are downsized and capacity increased by stacking more elements, the occupied area on the wiring board grows, making it difficult to secure sufficient pad arrangement regions for connections, especially with the controller element, leading to potential defective connections and increased laminate thickness.
Innovation Solution
The semiconductor device employs a step-like stacking configuration with alternating directions for semiconductor elements, using metallic wires for connections, and a sealing resin layer to integrate the elements while varying the thickness of lowermost elements to prevent defective bonding and maintain a compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked semiconductor elements is increased to provide high capacity, then the storage capacity is improved, but the occupied area on the wiring board increases
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stepped stacking, allowing multiple semiconductor elements to be arranged vertically in layers. This dimensional change enables high capacity storage while maintaining a compact footprint on the wiring board, as elements are stacked in multiple levels rather than spread out in a single plane.
Solution Approach 2:
The patent implements a nested stepped structure where semiconductor elements are stacked in overlapping layers, with each layer partially positioned on top of the previous layer. This nesting approach maximizes space utilization by allowing elements to share vertical space while maintaining electrical connectivity through wire bonding.
2Quantity of substance
If the number of stacked semiconductor elements is increased, then the storage capacity is improved, but the pad arrangement region becomes restricted
Solution Approach 1:
The patent divides the wiring board into multiple functional regions: element mounting sections for stacked semiconductor elements, separate pad arrangement regions for connection pads, and wire bonding regions. This segmentation allows the pad arrangement region to be optimized independently from the element stacking area, ensuring sufficient space for electrical connections while accommodating high-capacity stacked elements.
3Quantity of substance
If the stepped direction length becomes long with increased stacking, then the storage capacity is improved, but the occupied area increases
Solution Approach 1:
The patent employs asymmetric stepped stacking where semiconductor elements are arranged in non-uniform layers with varying offsets. Rather than uniform sequential stacking, the elements are positioned with different lateral displacements in each layer, creating a compact asymmetric structure that reduces the overall length in the stepped direction while maintaining high stacking density.
4Ease of manufacture
If uniform thickness is used for all semiconductor elements, then the manufacturing is simplified, but defective bonding may occur
Solution Approach 1:
The patent applies local quality by specifying that only the lowermost semiconductor element in each stacked group has increased thickness, while upper elements maintain uniform standard thickness. This localized thickness variation ensures reliable wire bonding at critical lower positions where mechanical stability is most important, while keeping the rest of the structure simple and manufacturable.
Data Source
AI summary
A plurality of semiconductor elements configuring a first element group are stacked in a step-like shape on a wiring board. A plurality of semiconductor elements configuring a second element group are stacked in a step-like shape on the first element group toward a direction opposite to the stepped direction of the first element group. The semiconductor elements are electrically connected to connection pads of the wiring board through metallic wires. Among the plurality of semiconductor elements configuring the second element group, the lowermost semiconductor element has a thickness larger than those of the other semiconductor elements.