Semiconductor Memory Strings With Stacked Source Lines
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Solution Overview
Problem
There is a need to increase data storage capacity in semiconductor devices while maintaining or improving electrical characteristics, as existing methods for reducing memory cell size and forming three-dimensional memory blocks face limitations in increasing memory cells within a predetermined area and suffer from deterioration of electrical characteristics.
Innovation Solution
A semiconductor device with first and second memory strings coupled between bit lines and a common source line, where the common source line includes a stacked structure of a conductive layer and a silicon layer, allowing for efficient data storage and improved electrical characteristics through a layered structure that enhances memory cell connectivity and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase data storage capacity, then the number of memory cells increases, but manufacturing precision and electrical characteristics deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, allowing significant increase in storage capacity without reducing individual cell size. The bit lines and source lines are extended vertically to connect memory cells across multiple layers, resolving the contradiction between increasing cell quantity and maintaining manufacturing precision.
Solution Approach 2:
The patent employs composite material structures including stacked conductive layers (e.g., tungsten, copper) and insulating layers (e.g., silicon oxide, silicon nitride) to form the three-dimensional memory architecture. The bit lines and source lines are constructed as composite structures with multiple material layers to ensure electrical integrity and mechanical stability in the vertical stacking configuration.
2Quantity of substance
If three-dimensional memory blocks are formed to increase storage capacity, then data storage capacity increases, but electrical characteristics deteriorate
Solution Approach 1:
The three-dimensional memory structure is segmented into multiple discrete layers with individual bit lines and source lines for each layer. This segmentation allows independent electrical control and optimization of each memory cell layer, preventing the deterioration of electrical characteristics that would result from treating the 3D structure as a monolithic block. Each layer can be independently accessed and operated.
Solution Approach 2:
The patent introduces intermediate conductive structures and insulation layers between stacked memory cell layers to maintain electrical isolation and signal integrity. These intermediary elements prevent electrical interference between adjacent layers while enabling vertical signal transmission, thus preserving electrical characteristics in the three-dimensional configuration.
3Quantity of substance
If more three-dimensional memory blocks are formed within a predetermined area, then storage capacity increases, but device complexity increases
Solution Approach 1:
The patent implements a universal three-dimensional memory block design where multiple memory blocks share common structural elements including bit line structures, source line structures, and insulation layer patterns. This multi-functional approach allows the same structural template to be replicated across multiple blocks, increasing storage capacity while minimizing the increase in device complexity through design standardization.
Data Source
AI summary
A semiconductor device includes first memory strings coupled between a first common source line formed on a substrate and bit lines formed over the first common source line, and second memory strings coupled between the bit lines and a second common source line formed over the bit lines, wherein each of the bit lines includes a stacked structure of a conductive layer and a silicon layer formed on the conductive layer.