3D Semiconductor Memory Stacking for Integration Density
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Solution Overview
Problem
The integration density of semiconductor devices is limited by the cost of advanced equipment and difficulties in fabrication processes, making three-dimensional semiconductor memory devices expensive and unreliable compared to two-dimensional devices.
Innovation Solution
The development of semiconductor devices with gate and insulation patterns repeatedly stacked on a substrate, featuring a through region with a channel structure having different semiconductor regions of varying grain sizes, and a data storage layer between the gate patterns, allowing for increased integration density through advanced patterning and heat treatment processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional semiconductor memory devices are produced to increase integration density, then integration density is improved, but manufacturing cost increases and reliability deteriorates
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory structures. Multiple memory cell layers are stacked along the vertical direction, with each layer containing memory cells formed by intersecting word lines and bit lines. This dimensional change allows significant increase in integration density without compromising reliability, as each stacked layer maintains standard two-dimensional cell structures that have proven reliable
2Productivity
If advanced fine pattern forming technology is used to increase integration density, then integration density is improved, but manufacturing cost increases
Solution Approach 1:
The manufacturing process is divided into multiple sequential stages: forming sacrificial patterns, creating through-holes, depositing semiconductor layers, removing sacrificial patterns, and forming final memory cell patterns. Each stage uses relatively simple patterning techniques that avoid the need for expensive advanced fine pattern forming equipment, while the cumulative effect achieves high integration density through vertical stacking
3Reliability
If channel structures with larger grain size are formed to improve device performance, then reliability is improved, but manufacturing process complexity increases
Solution Approach 1:
Different regions of the channel structure are given different grain sizes to optimize local performance. The channel structure includes a first semiconductor region with a first grain size and a second semiconductor region with a second grain size larger than the first. This local differentiation improves device performance in specific regions without requiring complex manufacturing processes for the entire structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances integration density and reduces costs by enabling more efficient use of substrate area, improving the reliability and performance of semiconductor memory devices.
Implementation Method 1
forming a second semiconductor layer having a grain size larger than the grain size of the first semiconductor layer by performing a heat treatment process
Data Source
AI summary
Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.