Semiconductor Memory Device Step-Like Electrode Formation
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Solution Overview
Problem
The existing methods for shaping the end of laminated electrodes in semiconductor memory devices into a step-like form are inefficient, requiring repeated cycles of resist slimming and reactive ion etching, which increases processing time and reduces throughput due to the need for multiple gas replacements.
Innovation Solution
A method involving the lamination of boron-doped silicon layers and non-doped sacrificial layers, where the end of the sacrificial layers is formed into a step-like structure through wet etching, allowing for the formation of step-like control gates and reducing the number of etching steps by using isotropic etching to create the desired shape.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If resist slimming and reactive ion etching are repeatedly carried out for each electrode layer to shape the end into a step-like form, then the step-like structure can be formed, but the processing time becomes longer and throughput is reduced due to multiple gas replacements
Solution Approach 1:
The patent divides the laminated electrode structure into multiple individual electrode layers, each with its own sacrificial layer. By processing each layer separately through wet etching rather than repeatedly applying RIE to the entire stack, the method reduces the number of gas replacements while maintaining the step-like structure formation capability.
Solution Approach 2:
The patent introduces sacrificial layers (made of materials like silicon oxide or silicon nitride) as intermediary structures between the electrode layers. These sacrificial layers enable the formation of step-like structures through wet etching processes, replacing the need for repeated RIE and resist slimming cycles, thereby improving throughput while maintaining manufacturing precision.
2Quantity of substance
If the number of laminations is increased to achieve higher integration, then the memory capacity is improved, but the number of gas replacements increases, making the etching time longer
Solution Approach 1:
The patent extracts the sacrificial layers from the final device structure, using them only as temporary intermediaries during fabrication. By removing these sacrificial layers after they have served their purpose in defining the step-like structures, the method enables high lamination counts without proportionally increasing processing time, as the sacrificial layer removal is done efficiently through wet etching.
Solution Approach 2:
The patent changes the etching parameters by switching from dry RIE to wet etching for the sacrificial layer removal process. This parameter change allows for faster and more efficient etching of the sacrificial layers, enabling the processing of highly laminated structures without excessive etching time, thus supporting increased memory capacity.
3Shape
If repeated resist slimming and RIE cycles are performed for each layer, then the step-like shape can be achieved, but the process complexity and manufacturing steps increase
Solution Approach 1:
The patent merges the formation of step-like structures across multiple electrode layers into a single wet etching process step, rather than performing separate RIE and resist slimming cycles for each layer. By combining these operations and using wet etching to remove sacrificial layers from multiple layers simultaneously, the method achieves the desired step-like shape while reducing overall process complexity.
Solution Approach 2:
The patent performs preliminary formation of sacrificial layers between electrode layers before the final etching step. This preliminary action allows the sacrificial layers to define the step-like structures during a single subsequent wet etching process, eliminating the need for repeated resist slimming and RIE cycles, thereby reducing the total number of manufacturing steps while achieving the required shape precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time, improves yields, and lowers process costs by minimizing the number of steps required in the fabrication process, while also enabling the use of inter-electrode insulating films as etching stoppers for forming contact holes.
Implementation Method 1
the end of the sacrificial layers is formed into a step-like structure through wet etching
Implementation Method 2
using isotropic etching to create the desired shape
Data Source
AI summary
According to one embodiment, a method of manufacturing a semiconductor memory device is provided. In the method, a laminated body in which a first silicon layer, a first sacrificial layer, a second silicon layer, and a second sacrificial layer are laminated in turn is formed. A first insulating film is formed on the laminated body. A trench is formed in the laminated body and the first insulating film. A third sacrificial layer is formed into the trench. The third sacrificial layer is etched by wet etching to be retreated from a top surface of the third sacrificial layer, thereby etching end faces of the first sacrificial layer and the second sacrificial layer.