Semiconductor Memory Device Stepwise Wiring Transistor Integration
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Solution Overview
Problem
In three-dimensional semiconductor memory devices, the increased number of memory cell laminations and conductive layers leads to a larger occupation area for transistors, necessitating a reduction in transistor area to enhance integration and downsizing.
Innovation Solution
The semiconductor memory device employs a stepwise wiring structure with conductive layers and peripheral transistors positioned above a substrate, where the channel portion of the transistor is aligned at the same height as the conductive layers, reducing the occupied area and allowing for high integration without additional space for peripheral transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of lamination of memory cells and conductive layers is increased to enhance storage capacity, then the storage capacity is improved, but the occupation area of transistors increases
Solution Approach 1:
The patent positions the channel portion of the peripheral transistor at the same height as the conductive layers, utilizing the vertical dimension to overlap the transistor with the conductive layers. This dimensional repositioning allows the transistor to share the same lateral footprint as the conductive layers, thereby preventing additional occupation area while accommodating increased lamination for higher storage capacity.
2Area of stationary object
If the occupation area of peripheral transistors is reduced to enable downsizing, then the device size is decreased, but the processing depth increases
Solution Approach 1:
The patent merges the vertical position of the channel portion with the conductive layers, aligning them at the same height. This merging of positions allows the transistor to be integrated within the existing vertical stack, reducing lateral occupation area while managing processing depth through shared spatial coordination rather than sequential layering.
3Area of stationary object
If the channel portion is positioned at the same height as conductive layers to reduce area, then the occupation area is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent forms the channel portion of the peripheral transistor at the same height as the conductive layers during the earlier stages of the manufacturing process, before finalizing the complete stack structure. This preliminary positioning establishes the spatial relationship early, allowing subsequent layers to be built around this established configuration, thereby reducing overall manufacturing complexity despite the unconventional positioning.
Data Source
AI summary
The semiconductor device according to the embodiments comprises: a plurality of first conductive layers arranged in a first direction above a substrate, the first direction intersecting an upper surface of the substrate; a semiconductor layer that faces a side surface of the plurality of first conductive layers and extends in the first direction as a longitudinal direction thereof; a wiring portion configured by causing end portions of the first conductive layers to be at different positions, respectively; and a transistor located above the wiring portion. The transistor comprises: a channel portion arranged at a same height as a second conductive layer, the second conductive layer being one of the plurality of the first conductive layers; agate insulating film arranged on an upper surface of the channel portion; and a gate electrode layer arranged on an upper surface of the gate insulating film.