Semiconductor Memory Device Sub-Bit Line Architecture
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Solution Overview
Problem
Ferroelectric memories face limitations in high-speed operation due to parasitic capacitance from series-connected cell transistors, which hinders downscaling and increases bit line capacitance, leading to reliability issues and operational delays.
Innovation Solution
The semiconductor memory device employs a configuration with sub-bit lines connected to bit lines, ferroelectric capacitors with a ferroelectric substance between electrodes, and cell transistors with gates connected to word lines, allowing for reduced parasitic capacitance and smaller cell sizes by eliminating bit line contacts between adjacent capacitors, and using a hierarchical bit line configuration to minimize capacitance addition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory cells are connected in series via bit lines, then the memory structure is simplified, but parasitic capacitance increases causing operational delays
Solution Approach 1:
The patent divides the memory array into multiple blocks (first memory cell block, second memory cell block, etc.) with each block having its own dedicated bit line connections. This segmentation prevents series connection of cell transistors across different blocks, reducing parasitic capacitance accumulation while maintaining structural organization.
Solution Approach 2:
The patent introduces plate lines as intermediary connections between cell transistors and ferroelectric capacitors. By routing signals through plate lines rather than directly through series cell transistors on bit lines, the parasitic capacitance effect is reduced and signal transmission speed is improved.
2Loss of time
If the number of series-connected memory cells is decreased, then parasitic capacitance is reduced, but chip area cannot be downscaled
Solution Approach 1:
The memory array is divided into multiple independent blocks, each with a limited number of series-connected cells. This allows reduction of parasitic capacitance within each block while maintaining high density through multiple blocks, achieving both speed and area efficiency.
Solution Approach 2:
The patent extends the memory structure in the vertical dimension by stacking multiple memory cell blocks and using plate lines that run perpendicular to bit lines. This three-dimensional arrangement increases storage capacity without increasing parasitic capacitance on individual bit lines.
3Area of moving object
If bit line contacts are eliminated between adjacent capacitors, then cell size is reduced, but connection complexity increases
Solution Approach 1:
The patent removes bit line contacts between adjacent ferroelectric capacitors, extracting this unnecessary connection element. This elimination reduces cell size and parasitic capacitance while the connection complexity is managed through the systematic block structure and plate line routing.
Solution Approach 2:
Instead of connecting adjacent capacitors directly through bit line contacts, the patent inverts the connection approach by using plate lines to connect cell transistors to capacitors, and using block selection transistors to access multiple cells through shared bit lines.
4Device complexity
If plate lines are shared among multiple memory cells, then device complexity is reduced, but reading/writing speed is limited by parasitic capacitance
Solution Approach 1:
The patent segments the memory into multiple blocks with dedicated plate line groups for each block. While plate lines are shared within blocks, the segmentation ensures that parasitic capacitance effects are localized and do not accumulate across the entire array, maintaining high-speed operation.
Solution Approach 2:
Block selection transistors serve as intermediaries between plate lines and individual cell transistors. This intermediary structure allows efficient signal distribution through shared plate lines while minimizing parasitic capacitance impact on signal transmission speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed operation, reduces bit line capacitance, improves memory cell reliability, and allows for downscaling while maintaining efficient logic embedded memory functionality, addressing the issues of parasitic capacitance and operational delays.
Implementation Method 1
ferroelectric capacitors each including a ferroelectric substance between two electrodes
Data Source
AI summary
A memory includes ferroelectric capacitors; cell transistors each including a drain connected to one electrode of each ferroelectric capacitor, and a gate connected to the word line; and memory cell blocks each including a reset transistor, a block selection transistor, and memory cells including the ferroelectric capacitors and the cell transistors, wherein sources of the cell transistors are connected to the plate lines, the other electrode of the ferroelectric capacitor is connected to one of the sub-bit lines, a source and a drain of the block selection transistor are connected to one of the sub-bit lines and one of the bit lines, a source of the reset transistor is connected to one of the plate lines or a fixed potential, and a drain of the reset transistor in each memory cell block is connected to one of the sub-bit lines, and the memory cell blocks configure a memory cell array.