Semiconductor Memory Sub-Column Lines Equalize Current Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving uniform current paths and resistance values across memory cells, leading to potential overcurrent issues and deterioration in memory cell characteristics due to varying current path lengths.
Innovation Solution
The semiconductor memory device incorporates sub-column and sub-row lines to equalize current path lengths by adjusting the positions of connection structures between column and row lines, ensuring that longer current paths on one line correspond to shorter paths on another, thereby maintaining consistent resistance across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory cells are arranged in a conventional grid structure with uniform row and column lines, then the device complexity is reduced and manufacturing is simplified, but the current path lengths vary significantly across different memory cells leading to non-uniform resistance values and overcurrent issues
Solution Approach 1:
The memory device is divided into multiple memory blocks, each containing memory cells arranged in a specific pattern. Sub-column lines are introduced to segment the current path into controlled segments, allowing precise control over current path length within each block while maintaining overall device simplicity through modular organization.
Solution Approach 2:
Different regions of the memory device are designed with locally optimized current path configurations. Memory cells in different blocks have different current path lengths deliberately designed to achieve uniform resistance values across the entire device, with each local region tailored to compensate for position-dependent variations.
2Reliability
If the current path length is made uniform across all memory cells, then resistance values become consistent and overcurrent is prevented, but the device structure becomes more complex requiring additional sub-column lines and connection structures
Solution Approach 1:
The column lines are segmented into main column lines and sub-column lines, where sub-column lines connect to specific memory cells to control their current path length. This segmentation allows reliable current control for each memory cell while keeping the overall structure manageable through systematic organization of the segmented components.
Solution Approach 2:
Sub-column lines act as intermediary elements between the main column lines and memory cells. These intermediary structures enable precise control of current path length without requiring direct complex connections between all column lines and memory cells, thus achieving reliable operation with reduced structural complexity.
3Manufacturing precision
If additional sub-column lines and connection structures are added to equalize current paths, then manufacturing precision of current path length is improved, but the device complexity and fabrication process become more difficult
Solution Approach 1:
The fabrication process is segmented into standardized stages for forming main column lines, sub-column lines, and connection structures. Each segment follows a repeatable pattern that simplifies the manufacturing process despite the increased precision requirements, allowing mass production with controlled complexity.
Solution Approach 2:
The design utilizes parameter variations in the sub-column line positions and lengths to achieve precise current path control. By systematically varying these parameters according to a defined pattern, the manufacturing process achieves high precision without requiring complex custom fabrication steps for each memory cell.
Data Source
AI summary
Provided herein may be an electronic device including a semiconductor memory. The semiconductor memory may include: first column lines and sub-column lines extending in a first direction; first row lines extending in a second direction; first tiles including first memory cells connected between the first column lines and the first row lines; first contact plugs coupled to the sub-column lines and disposed between the first tiles in the first direction; second contact plugs coupled to the first row lines and disposed between the first tiles in the second direction; and a first connection structure partially coupling the first column lines to the sub-column lines such that the longer a current path on a first row line from a selected first memory cell to the corresponding second contact plug, the shorter a current path from the selected first memory cell to the corresponding first contact plug.