Semiconductor Memory Test Circuit for Parallel Bank Operations
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Solution Overview
Problem
Conventional semiconductor memory tests on merged DRAM/logic LSI devices are time-consuming and costly due to the limited number of terminals for data exchange with multi-bit bus widths, requiring multiple operations for data write and read.
Innovation Solution
A semiconductor memory and testing method that includes a memory cell array, control circuit, and data input/output circuit capable of writing and reading identical data simultaneously to and from multiple memory cells, utilizing a coincidence detection circuit and data compression circuit to reduce testing time and cost by enabling simultaneous operations and data compression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is written to memory cells using conventional sequential operations with limited terminals, then data exchange is possible, but test time increases significantly
Solution Approach 1:
The memory cell array is divided into multiple banks (first bank, second bank, third bank, fourth bank), each capable of independent simultaneous operation. This segmentation allows parallel data write operations to different banks using the same limited terminals, thereby reducing overall test time without requiring additional terminals.
Solution Approach 2:
Multiple data write operations that would normally be performed sequentially are merged into a single simultaneous operation by directing different data to different memory banks at the same time. This combining of operations reduces the total number of操作步骤 while using the existing terminal infrastructure.
2Loss of time
If multiple data read operations are performed sequentially from memory cells, then data can be read, but test time and cost increase
Solution Approach 1:
The memory system is segmented into multiple banks that can be read simultaneously. The control circuit is designed to generate read signals for multiple banks at the same time, enabling parallel data retrieval and significantly reducing test time compared to sequential reading.
Solution Approach 2:
The system maintains continuous useful action by performing data read operations on multiple banks simultaneously rather than waiting for one read operation to complete before starting the next. This continuous parallel operation maximizes productivity and reduces test time.
3Productivity
If identical data is written to multiple memory cells simultaneously, then test efficiency improves, but control circuit complexity increases
Solution Approach 1:
The control circuit is pre-configured with logic to generate simultaneous write signals for multiple banks when test mode is detected. This preliminary design allows identical data to be written to multiple memory cells at the same time without requiring complex real-time control decisions during the actual test operation.
Solution Approach 2:
The control circuit automatically detects when test mode is active and self-configures to perform simultaneous write operations to multiple banks. This self-service capability reduces the need for external complex control mechanisms while maintaining high test efficiency.
Data Source
AI summary
Upon conduct of a test on a semiconductor memory in a merged LSI or the like, data signals from a small data bus width are simultaneously written to a plurality of memory cells of a memory core. Then, a coincidence detection circuit makes a comparison between data read from the plurality of memory cells in expectation of a coincidence thereof. When the coincidence detection circuit detects the coincidence of the data, a data compression circuit compresses the compared data, and then outputs the compressed data. On the other hand, when the coincidence detection circuit detects an anticoincidence of the data, the data compression circuit converts the different data into fixed data, and then outputs the converted data.