Semiconductor Memory Circuit Test Pattern Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor integrated circuit testing methods require separate test patterns for each repair code, leading to increased costs due to the need for sufficient pattern storage capacity to accommodate all possible shift patterns, especially when detecting delay faults in memory circuits with redundant configurations.
Innovation Solution
A semiconductor integrated circuit design that includes a memory circuit with redundant cells, a fuse circuit for determining repair logic, a scan-designed register for stuck-at fault testing, and a decoding circuit that controls switching circuits to bypass faulty cells, allowing for unified test patterns for both stuck-at and delay faults without relying on specific repair codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate test patterns are generated for each repair code to detect delay faults, then testing accuracy is improved, but pattern storage capacity requirements increase and testing costs increase
Solution Approach 1:
The patent creates a universal test pattern that can detect both stuck-at faults and delay faults regardless of the repair code. The test pattern generation method is designed to work with any repair code configuration, making the testing system multi-functional and eliminating the need for separate patterns for each repair code scenario.
Solution Approach 2:
The patent changes the approach from storing multiple fixed patterns to dynamically generating test patterns based on circuit parameters. By modifying how test patterns are created rather than stored, the system adapts to different repair codes without requiring proportional increases in storage capacity.
2Measurement precision
If separate test patterns are generated for each repair code to detect delay faults, then testing accuracy is improved, but testing costs increase
Solution Approach 1:
The patent creates a universal test pattern that can detect both stuck-at faults and delay faults regardless of the repair code. The test pattern generation method is designed to work with any repair code configuration, making the testing system multi-functional and eliminating the need for separate patterns for each repair code scenario.
Solution Approach 2:
Instead of creating and storing unique test patterns for each repair code, the patent uses a single template or generator that can produce the necessary test sequences on-demand. This copying approach allows the same generation logic to serve multiple repair code scenarios without duplication of storage resources.
3Measurement precision
If a scan design is provided to the fuse register to test stuck-at faults, then stuck-at fault detection is improved, but the ability to generate delay fault test patterns without repair codes is reduced
Solution Approach 1:
The patent segments the testing functionality by introducing a register selection circuit that can independently select between the scan-designed fuse register for stuck-at fault testing and a separate mechanism for delay fault testing. This segmentation allows both testing capabilities to coexist without interfering with each other's functionality.
Solution Approach 2:
The register selection circuit acts as an intermediary that manages the interaction between the scan-designed fuse register and the delay fault test pattern generation. It mediates between the two testing approaches, allowing the system to switch between them as needed and enabling delay fault testing without being constrained by repair code dependencies.
Data Source
AI summary
A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first register and an output of the second register are connected, a memory bypass circuit which is located between a first switching circuit and a second switching circuit, and connected to the inputs and the outputs of the memory circuit. The register selection circuit is switched to the output signals of the first register when performing testing by way of the memory circuit, and switched to output signals of the second register when performing testing by way of the memory bypass circuit.