3D Semiconductor Memory Device With Through-Via Spacer Films
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration density due to the limitations of two-dimensional designs, which require expensive equipment for miniaturization, leading to insufficient integration density and higher costs.
Innovation Solution
A semiconductor memory device design featuring a three-dimensional structure with through-vias and spacer films that connect conductive patterns across multiple layers, enhancing integration density without the need for additional fabrication regions, thus improving productivity and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar design is used, then manufacturing process is simpler, but integration density is insufficient
Solution Approach 1:
The patent transitions from a two-dimensional planar design to a three-dimensional structure by stacking multiple layers (first substrate, mold structure with gate electrodes, second substrate) vertically. This dimensional change enables higher integration density without complicating the manufacturing process, as the through-via formation and spacer film deposition are extensions of existing fabrication techniques into the vertical domain.
2Quantity of substance
If pattern miniaturization is pursued, then integration density increases, but expensive apparatuses are required
Solution Approach 1:
Instead of pursuing further pattern miniaturization in the lateral direction which would require expensive lithography equipment, the patent achieves integration density improvement by stacking structures vertically. The through-vias and spacer films enable this vertical integration using relatively standard fabrication processes, avoiding the need for ultra-expensive miniaturization apparatuses.
Solution Approach 2:
The patent employs a nested structure where the first substrate contains memory cells, the mold structure with gate electrodes is stacked on top, and the second substrate with circuit elements is placed on the mold structure. Through-vias penetrate through these nested layers to establish electrical connections, enabling high integration without lateral miniaturization.
3Quantity of substance
If through-vias are added to connect multiple layers, then integration density increases, but fabrication complexity increases
Solution Approach 1:
The patent forms spacer films on the side surfaces of through-via trenches before filling them with conductive patterns. This preliminary action of creating spacers simplifies the overall fabrication process by defining the through-via geometry and electrical isolation requirements in advance, reducing the need for additional complex processing steps later.
Solution Approach 2:
The spacer films automatically provide electrical isolation between the conductive patterns in through-vias and the surrounding structures (first substrate, mold structure). This self-service function of the spacers eliminates the need for additional isolation processing steps, simplifying the fabrication process while enabling high integration density.
Data Source
AI summary
A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure.