3D Semiconductor Memory Device With Trench-Defined Active Patterns
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Solution Overview
Problem
Semiconductor memory devices face challenges in increasing integration density and reliability due to increased resistance of memory cells and manufacturing process margins.
Innovation Solution
A semiconductor memory device design featuring a semiconductor substrate with trench-defined active patterns, device isolation layers, word lines, bit lines, and source lines, along with conductive pads and contact plugs, which enhances integration density and reliability by improving contact areas and electrical separation of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are further miniaturized to increase integration density, then integration density is improved, but manufacturing process margins are reduced and resistance increases
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a 3D vertical architecture where active patterns extend in the depth direction beneath isolation regions. This dimensional change allows memory cells to be stacked vertically, increasing integration density without further miniaturizing the lateral footprint, thereby preserving manufacturing process margins.
Solution Approach 2:
The patent implements nested structures where active patterns are positioned beneath isolation regions, and conductive plugs are embedded within contact holes that penetrate through multiple layers. This nesting approach maximizes space utilization in the vertical dimension, enabling higher integration density while maintaining manufacturability.
2Quantity of substance
If memory cells are further miniaturized to increase integration density, then integration density is improved, but resistance of memory cells increases
Solution Approach 1:
By moving to 3D vertical architecture, the patent extends conductive paths in the depth direction rather than compressing them laterally. This allows for optimized conductor cross-sectional areas and lengths independently, enabling better resistance control even as integration density increases through vertical stacking.
Solution Approach 2:
The patent employs asymmetric conductor dimensions where the cross-sectional area and length of conductive paths are independently optimized. This asymmetry allows tailored resistance optimization for each memory cell configuration, decoupling resistance from integration density constraints.
3Ease of manufacture
If active patterns are arranged in a 2D plane to simplify manufacturing, then ease of manufacture is improved, but integration density is limited
Solution Approach 1:
The patent extends the manufacturing approach into the third vertical dimension by forming active patterns that protrude from the substrate surface and positioning conductive plugs at multiple height levels. This 3D manufacturing approach maintains process simplicity while dramatically increasing integration density compared to 2D planar arrangements.
Solution Approach 2:
The patent forms active patterns and isolation regions in a predetermined vertical sequence before forming conductive plugs and word lines. This preliminary structuring simplifies subsequent manufacturing steps while enabling complex 3D memory cell arrangements that would be difficult to achieve with conventional 2D approaches.
4Quantity of substance
If memory cells are closely spaced to increase integration density, then integration density is improved, but electrical separation between cells is reduced leading to write/read errors
Solution Approach 1:
The patent achieves electrical separation in the vertical dimension by positioning active patterns at different depth levels and using isolation regions that extend vertically between adjacent memory cells. This 3D separation mechanism maintains cell isolation even when lateral spacing is minimized for high integration density.
Solution Approach 2:
The patent divides the memory cell array into independently controllable units with distinct active patterns, isolation regions, and conductive plugs for each cell. This segmentation allows precise electrical control and isolation of individual cells, preventing cross-talk and write/read errors even in densely packed configurations.
Data Source
AI summary
A semiconductor memory device includes a device isolation in a trench that defines first to third active patterns that are spaced apart from each other and having a long axis parallel to a first direction, first and second word lines extending in a second direction perpendicular to the first direction, a bit line, and a source line. The first and second active patterns are arranged in the second direction to constitute a column. The third active pattern is at a side of the column. The first word line intersects the first and second active patterns. The second word line intersects the third active pattern. When viewed from a plan view, the bit line extends in the first direction between the first and third active patterns, and the source line extends in the first direction between the second and third active patterns.