Semiconductor Memory Apparatus TSV Stacking Area Optimization
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Solution Overview
Problem
The increase in prefetch rate in semiconductor memory apparatuses leads to a significant increase in the number of main amplifiers and global input/output lines, resulting in a substantial sacrifice of core area, which limits the implementation of high-speed semiconductor memory devices.
Innovation Solution
The semiconductor memory apparatus incorporates a through-silicon via (TSV) structure with a switching unit that selectively outputs half of the data signals from bit line sense amplifiers, reducing the number of main amplifiers and global input/output lines while maintaining the same prefetch rate by stacking multiple chips, thereby optimizing the core area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the prefetch rate is increased to enhance data output bandwidth, then the data processing rate is improved, but the number of main amplifiers and global input/output lines increases, resulting in increased core area occupation
Solution Approach 1:
The invention divides the bit line sense amplifiers into multiple groups and segments the local input/output lines accordingly. By selectively activating only the required segments based on the prefetch rate, the system achieves high data processing rates without proportionally increasing the total number of main amplifiers and global I/O lines, thus reducing core area occupation.
Solution Approach 2:
The invention introduces a new dimensional approach by adding a switching unit that controls the connection between local and global I/O lines. This switching layer enables dynamic reconfiguration of the data path, allowing the same physical infrastructure to support higher prefetch rates without linearly increasing the number of amplifiers and global lines.
2Productivity
If the number of main amplifiers and global input/output lines is increased to support higher prefetch rates, then the data output bandwidth is enhanced, but the current consumption increases
Solution Approach 1:
The invention implements partial action by activating only the necessary portion of bit line sense amplifiers and global I/O lines based on the current prefetch rate requirement. The switching unit enables selective activation, so when operating at lower prefetch rates, fewer amplifiers and I/O lines are active, thereby reducing current consumption while still supporting the capability for higher prefetch rates when needed.
3Quantity of substance
If the core area is reduced to accommodate more memory cells, then the memory capacity is improved, but the number of main amplifiers and global input/output lines must be reduced, limiting the prefetch rate
Solution Approach 1:
The invention introduces dynamic reconfiguration capability through the switching unit, which can adaptively adjust the number of active global I/O lines based on the prefetch rate requirement. This dynamic approach allows the system to maintain high memory capacity with fewer permanent global I/O lines while still achieving high prefetch rates when needed, as the same infrastructure can be dynamically reconfigured for different operating modes.
Data Source
AI summary
A semiconductor memory apparatus includes: a memory cell array including a plurality of memory cells; a bit line sense amplifier (BLSA) coupled to the memory cells in the memory cell array through a bit line; a plurality of local input/output lines coupled to the BLSA; and a switching unit coupled to the local input/output lines and configured to select a part of the local input/output lines.