Semiconductor Memory Two-Stage Programming for Data Reliability
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in reliably storing multiple-bit data due to the complexity of threshold voltage distributions and the need for efficient programming schemes that minimize data disturbance.
Innovation Solution
The semiconductor memory employs a two-stage write operation with a single-pulse scheme in the first stage and a double-pulse scheme in the second stage, using different program pulses to classify and program memory cells, thereby adjusting threshold voltages and improving data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-pulse programming scheme is used, then the programming process is simple and fast, but the threshold voltage distribution becomes complex and data reliability deteriorates
Solution Approach 1:
The programming process is divided into two distinct stages: a first programming stage that applies a first program pulse to establish an initial threshold voltage distribution, and a second programming stage that applies a second program pulse with different characteristics to refine the distribution. This segmentation allows each stage to be optimized for its specific function, achieving both speed and reliability.
Solution Approach 2:
The invention dynamically adjusts programming parameters between stages. The second program pulse has different characteristics (such as duration, amplitude, or waveform) compared to the first program pulse, allowing the system to adapt the programming approach based on the state of the memory cells after the first stage, thereby optimizing both speed and reliability.
2Quantity of substance
If multiple-bit data is stored in each memory cell, then the storage capacity increases, but the threshold voltage distribution complexity increases and data disturbance occurs
Solution Approach 1:
The two-stage programming approach segments the complex task of programming multiple-bit data into manageable steps. The first stage programs a subset of the data bits, establishing a preliminary threshold voltage distribution, while the second stage programs the remaining bits and refines the overall distribution, reducing the complexity handled at any one time and minimizing data disturbance.
Solution Approach 2:
The invention changes programming parameters between stages to optimize for different aspects of multiple-bit programming. By adjusting pulse characteristics in the second stage based on the results of the first stage, the system can accurately control the final threshold voltage distribution for multiple-bit storage while minimizing unwanted data disturbance.
3Manufacturing precision
If a double-pulse programming scheme is used, then the threshold voltage distribution is controlled accurately, but the programming process becomes complex and time-consuming
Solution Approach 1:
The programming scheme is segmented into two stages with distinct functions. The first stage handles the bulk of the programming task with a simpler pulse, while the second stage applies a more precise pulse for fine-tuning. This segmentation reduces overall complexity compared to applying a complex double-pulse sequence to every cell, as the second stage only needs to operate on cells that require refinement.
Solution Approach 2:
The second program pulse is applied selectively based on the state of memory cells after the first stage. Not all cells require the same programming treatment, and the system can identify and apply the second pulse only where needed, reducing the effective complexity of the programming process while maintaining high precision where required.
4Reliability
If verification is performed after programming, then data reliability is improved, but the overall write time increases
Solution Approach 1:
The first programming stage acts as a preliminary action that programs memory cells to a sufficient degree before the second stage. This preliminary programming reduces the amount of refinement needed in the second stage, allowing verification to be performed more efficiently and reducing the total time required while maintaining reliability.
Solution Approach 2:
By changing programming parameters between stages, the system optimizes the balance between programming speed and accuracy. The first stage uses parameters optimized for speed, while the second stage uses parameters optimized for precision, allowing verification to be performed with less additional time while achieving the required reliability.
Data Source
AI summary
According to one embodiment, a semiconductor memory of an embodiment includes memory cells, a word line, bit lines, and a controller. The word line is coupled to a plurality of memory cells. The plurality of bit lines are respectively coupled to the plurality of memory cells. The controller executes a first write, and classifies a plurality of memory cells to which the second data should be written into a plurality of subgroups in accordance with a result of the first write, and after the classification, the controller executes a second write that includes a first program loop.